urecpe

Vector Unsigned Reciprocal Estimate

URECPE <Vd>.<T>, <Vn>.<T>

Estimates reciprocal for unsigned integers.

Pseudocode Operation

if size == 0b10 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← UnsignedReciprocalEstimate(Vn[i])

Example

URECPE v0.4s.T, v1.4s.T

Encoding

Binary Layout

011101

28:23

10000

21:17

11100

16:12

11:10

9:5

4:0

Format SIMD Two Register

Opcode 0x0EA1C800

Extension NEON (SIMD)

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0EA1C800	URECPE <Vd>.<T>, <Vn>.<T>		A64		0 \| Q \| 0 \| 011101 \| sz \| 10000 \| 11100 \| 10 \| Rn \| Rd
0x4400A000	URECPE <Zd>.S, <Pg>/M, <Zn>.S		A64		01000100 \| size \| 00 \| 0 \| 0 \| 0 \| 0 \| 101 \| Pg \| Zn \| Zd

Description

Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(32) element;

for e = 0 to elements-1
    element = Elem[operand, e, 32];
    Elem[result, e, 32] = UnsignedRecipEstimate(element);

V[d, datasize] = result;