revb

SVE Reverse Bytes in Elements

REVB <Zd>.<T>, <Pg>/M, <Zn>.<T>

Reverses bytes within 16/32/64-bit elements.

Details

Reverses the byte order within each element of a SVE vector under predicate control; for 16-bit elements 2 bytes are reversed, for 32-bit elements 4 bytes, and for 64-bit elements 8 bytes. This instruction operates only in AArch64 state and does not modify the condition flags.

Pseudocode Operation

elements ← VL / esize
for i = 0 to elements - 1
  if Pg[i] then
    Zd[i] ← ReverseBytes(Zn[i], esize)
  else
    Zd[i] ← Zd[i]

Example

REVB z0.s.T, p0/m/M, z1.s.T

Encoding

Binary Layout
00000101
size
1001
0
0
100
Pg
Zn
Zd
 
Format SVE Permute
Opcode 0x05248000
Extension SVE

Operands

  • Zd
    Destination scalable vector register (SVE)
  • Pg
    Mask
  • Zn
    First source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05248000 REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 00000101 | size | 1001 | 0 | 0 | 100 | Pg | Zn | Zd

Description

Reverse the order of 8-bit bytes, 16-bit halfwords or 32-bit words within each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = Reverse(element, swsize);

Z[d, VL] = result;