ldrab

Load Register Authenticate (Key B)

LDRAB <Xt>, [<Xn|SP>, #<simm>]

Loads a value, authenticating the address with Key B.

Details

Loads a 64-bit value from memory using an address authenticated with Pointer Authentication Code (PAC) using Key B. The address is computed from a base register and a signed 9-bit immediate offset. This AArch64-only instruction requires PAC support and will generate an Authentication Failure exception if authentication fails; no condition flags are affected.

Pseudocode Operation

address ← Xn|SP + (simm9 << 3)
authenticated_address ← AuthenticateAddressB(address)
Xt ← [authenticated_address]

Example

LDRAB x3, [x1, #-8]

Encoding

Binary Layout
11
111
0
00
1
S
1
imm9
0
1
Rn
Rt
 
Format Load/Store
Opcode 0xF8A00400
Extension PAC (Security)

Operands

  • Xt
    Transfer 64-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • simm
    Signed immediate offset

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF8A00400 LDRAB <Xt>, [<Xn|SP>{, #<simm>}] A64 11 | 111 | 0 | 00 | 1 | S | 1 | imm9 | 0 | 1 | Rn | Rt
0xF8A00C00 LDRAB <Xt>, [<Xn|SP>{, #<simm>}]! A64 11 | 111 | 0 | 00 | 1 | S | 1 | imm9 | 1 | 1 | Rn | Rt

Description

Load Register, with pointer authentication. This instruction authenticates an address from a base register using a modifier of zero and the specified key, adds an immediate offset to the authenticated address, and loads a 64-bit doubleword from memory at this resulting address into a register. Key A is used for LDRAA. Key B is used for LDRAB. If the authentication passes, the PE behaves the same as for an LDR instruction. For information on behavior if the authentication fails, see Faulting on pointer authentication. The authenticated address is not written back to the base register, unless the pre-indexed variant of the instruction is used. In this case, the address that is written back to the base register does not include the pointer authentication code. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(64) data;
boolean privileged = PSTATE.EL != EL0;
boolean wb_unknown = FALSE;

AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, tagchecked);
if wback && n == t && n != 31 then
    Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
    assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
    case c of
        when Constraint_WBSUPPRESS wback = FALSE;    // writeback is suppressed
        when Constraint_UNKNOWN    wb_unknown = TRUE;    // writeback is UNKNOWN
        when Constraint_UNDEF      UNDEFINED;
        when Constraint_NOP        EndOfInstruction();

if n == 31 then
    address = SP[];
else
    address = X[n, 64];


if use_key_a then
    address = AuthDA(address, X[31, 64], TRUE);
else
    address = AuthDB(address, X[31, 64], TRUE);

if n == 31 then
    CheckSPAlignment();

address = GenerateAddress(address, offset, accdesc);
data = Mem[address, 8, accdesc];
X[t, 64] = data;

if wback then
    if wb_unknown then
        address = bits(64) UNKNOWN;
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;