ARM Opcode Map
Reverse lookup instructions by their hexadecimal encoding.
| Opcode | Mnemonic | Syntax | Format | Name |
|---|---|---|---|---|
| 0x0416A000 | abs | ABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Integer Unary | SVE Absolute Value |
| 0x0E20B800 | abs | ABS <Vd>.<T>, <Vn>.<T> | SIMD Two Register | Vector Absolute Value |
| 0x1A000000 | adc | ADC <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Add with Carry |
| 0x9A000000 | adc | ADC <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Add with Carry (64-bit) |
| 0x00A00000 | adc | ADC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | Add with Carry (A32) |
| 0xEB400000 | adc.w | ADC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | Add with Carry (Wide) |
| 0x3A000000 | adcs | ADCS <Wd>, <Wn>, <Wm> | Data Processing (3-source) | Add with Carry and Set Flags |
| 0xBA000000 | adcs | ADCS <Xd>, <Xn>, <Xm> | Data Processing (3-source) | Add with Carry and Set Flags (64-bit) |
| 0x0B200000 | add | ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Add (Extended Register) |
| 0x8B200000 | add | ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Add (Extended Register 64-bit) |
| 0x11000000 | add | ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Add (Immediate) |
| 0x91000000 | add | ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Add (Immediate 64-bit) |
| 0x0B000000 | add | ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Add (Shifted Register) |
| 0x8B000000 | add | ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Add (Shifted Register 64-bit) |
| 0x0E208400 | add | ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Add (Integer) |
| 0x04000000 | add | ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Integer Binary | SVE Integer Add (Predicated) |
| 0x00800000 | add | ADD{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | Add (A32) |
| 0xEB000000 | add.w | ADD.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | Add (Wide) |
| 0x91800000 | addg | ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | Data Processing | Add with Tag |
| 0x5E31B800 | addp | ADDP <Dd>, <Vn>.<T> | NEON Scalar | Scalar Add Pairwise |
| 0x0E20BC00 | addp | ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Add Pairwise |
| 0x2B200000 | adds | ADDS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} | Data Processing (Register) | Add and Set Flags (Extended Register) |
| 0xAB200000 | adds | ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} | Data Processing (Register) | Add and Set Flags (Extended Register 64-bit) |
| 0x31000000 | adds | ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Add and Set Flags (Immediate) |
| 0xB1000000 | adds | ADDS <Xd>, <Xn|SP>, #<imm> {, lsl #<shift>} | Data Processing (Immediate) | Add and Set Flags (Immediate 64-bit) |
| 0x2B000000 | adds | ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Data Processing (Register) | Add and Set Flags (Shifted Register) |
| 0xAB000000 | adds | ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Data Processing (Register) | Add and Set Flags (Shifted Register 64-bit) |
| 0x0E31B800 | addv | ADDV <V><d>, <Vn>.<T> | SIMD Across Lane | Vector Add Across |
| 0x10000000 | adr | ADR <Xd>, <label> | PC-rel | Form PC-relative Address |
| 0xA000 | adr | ADR <Rd>, <label> | Thumb Data Proc | Form PC-relative Address (Thumb) |
| 0x028F0000 | adr | ADR<c> <Rd>, <label> | Data Proc | Form PC-relative Address (A32) |
| 0xF20F0000 | adr.w | ADR.W <Rd>, <label> | Thumb Data Proc | Form PC-relative Address (Wide) |
| 0x90000000 | adrp | ADRP <Xd>, <label> | PC-rel | Form PC-relative Address to 4KB Page |
| 0xF3B00340 | aesd | AESD.8 <Qd>, <Qm> | Crypto 2-Reg | AES Decrypt (A32) |
| 0x4E285800 | aesd | AESD <Vd>.16B, <Vm>.16B | Crypto | AES Decrypt (A64) |
| 0x4E285800 | aesd | AESD <Vd>.<T>, <Vn>.<T> | Crypto | AES Decrypt |
| 0xF3B00300 | aese | AESE.8 <Qd>, <Qm> | Crypto 2-Reg | AES Encrypt (A32) |
| 0x4E284800 | aese | AESE <Vd>.16B, <Vm>.16B | Crypto | AES Encrypt (A64) |
| 0x4E284800 | aese | AESE <Vd>.<T>, <Vn>.<T> | Crypto | AES Encrypt |
| 0xF3B003C0 | aesimc | AESIMC.8 <Qd>, <Qm> | Crypto 2-Reg | AES Inverse Mix Columns (A32) |
| 0x4E287800 | aesimc | AESIMC <Vd>.<T>, <Vn>.<T> | Crypto | AES Inverse Mix Columns |
| 0xF3B00380 | aesmc | AESMC.8 <Qd>, <Qm> | Crypto 2-Reg | AES Mix Columns (A32) |
| 0x4E286800 | aesmc | AESMC <Vd>.<T>, <Vn>.<T> | Crypto | AES Mix Columns |
| 0x12000000 | and | AND <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Bitwise AND (Immediate) |
| 0x92000000 | and | AND <Xd|SP>, <Xn>, #<imm> | Logical (Immediate) | Bitwise AND (Immediate 64-bit) |
| 0x0A000000 | and | AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND (Shifted Register) |
| 0x8A000000 | and | AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND (Shifted Register 64-bit) |
| 0x0E201C00 | and | AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Bitwise AND |
| 0x041A0000 | and | AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE Bitwise AND (Predicated) |
| 0x00000000 | and | AND{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | Bitwise AND (A32) |
| 0xEA000000 | and.w | AND.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | Bitwise AND (Wide) |
| 0x72000000 | ands | ANDS <Wd>, <Wn>, #<imm> | Logical (Immediate) | Bitwise AND and Set Flags (Immediate) |
| 0xF2000000 | ands | ANDS <Xd>, <Xn>, #<imm> | Logical (Immediate) | Bitwise AND and Set Flags (Immediate 64-bit) |
| 0x6A000000 | ands | ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND and Set Flags (Shifted Register) |
| 0xEA000000 | ands | ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise AND and Set Flags (Shifted Register 64-bit) |
| 0x041A2000 | andv | ANDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE Bitwise AND Reduction |
| 0x13007C00 | asr | ASR <Wd>, <Wn>, #<shift> | Data Processing (Immediate) | Arithmetic Shift Right (Immediate) |
| 0x9340FC00 | asr | ASR <Xd>, <Xn>, #<shift> | Data Processing (Immediate) | Arithmetic Shift Right (Immediate 64-bit) |
| 0x1AC02800 | asr | ASR <Wd>, <Wn>, <Wm> | Data Processing (Register) | Arithmetic Shift Right (Register) |
| 0x9AC02800 | asr | ASR <Xd>, <Xn>, <Xm> | Data Processing (Register) | Arithmetic Shift Right (Register 64-bit) |
| 0x04108000 | asr | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Shift | SVE Arithmetic Shift Right (Predicated) |
| 0x01A00050 | asr | ASR{S}<c> <Rd>, <Rm>, <Rs> | Data Proc | Arithmetic Shift Right (A32) |
| 0xD5087800 | at | AT S1E1R, <Xt> | System | Address Translate (Stage 1 Current) |
| 0xD5087800 | at | AT S1E1W, <Xt> | System | Address Translate (Stage 1 Write) |
| 0xD5087800 | at | AT <op>, <Xt> | System Alias | Address Translate |
| 0xDAC11800 | autda | AUTDA <Xd>, <Xn> | Data Processing | Authenticate Data Address (Key A) |
| 0xDAC11C00 | autdb | AUTDB <Xd>, <Xn> | Data Processing | Authenticate Data Address (Key B) |
| 0xDAC11000 | autia | AUTIA <Xd>, <Xn|SP> | Data Processing | Authenticate Code (Inst A) |
| 0xDAC11000 | autia | AUTIA <Xd>, <Xn> | Data Processing | Authenticate Instruction Address (Key A) |
| 0xDAC11400 | autib | AUTIB <Xd>, <Xn|SP> | Data Processing | Authenticate Code (Inst B) |
| 0xDAC11400 | autib | AUTIB <Xd>, <Xn> | Data Processing | Authenticate Instruction Address (Key B) |
| 0x14000000 | b | B <label> | Branch | Branch |
| 0x0A000000 | b | B<c> <label> | Branch | Branch (A32) |
| 0x54000000 | b.cond | B.cond <label> | Branch | Branch Conditional |
| 0xF0009000 | b.w | B.W <label> | Thumb Branch | Branch (Wide) |
| 0x54000010 | bc.cond | BC.cond <label> | Branch | Branch Consistent Conditional |
| 0x65000000 | bfadd | BFADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | BFloat16 Add |
| 0xF36F0000 | bfc | BFC <Rd>, #<lsb>, #<width> | Thumb Bitfield | Bit Field Clear (Thumb) |
| 0x07C0001F | bfc | BFC<c> <Rd>, #<lsb>, #<width> | Data Proc | Bit Field Clear |
| 0x0EA16800 | bfcvtn | BFCVTN <Vd>.<Tb>, <Vn>.<Ta> | NEON 2-Reg | BFloat16 Convert Narrow (NEON) |
| 0x0EA16800 | bfcvtn2 | BFCVTN2 <Vd>.<Tb>, <Vn>.<Ta> | NEON 2-Reg | BFloat16 Convert Narrow High (NEON) |
| 0x2E40FC00 | bfdot | BFDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | BFloat16 Dot Product (NEON) |
| 0xF3600000 | bfi | BFI <Rd>, <Rn>, #<lsb>, #<width> | Thumb Bitfield | Bit Field Insert (Thumb) |
| 0x07C00010 | bfi | BFI<c> <Rd>, <Rn>, #<lsb>, #<width> | Data Proc | Bit Field Insert |
| 0x33000000 | bfm | BFM <Wd>, <Wn>, #<immr>, #<imms> | Bitfield | Bitfield Move |
| 0xB3400000 | bfm | BFM <Xd>, <Xn>, #<immr>, #<imms> | Bitfield | Bitfield Move (64-bit) |
| 0x65068000 | bfmax | BFMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | BFloat16 Maximum |
| 0x65078000 | bfmin | BFMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | BFloat16 Minimum |
| 0x6E40EC00 | bfmmla | BFMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | NEON 3-Reg | BFloat16 Matrix Multiply-Accumulate (NEON) |
| 0x65028000 | bfmul | BFMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | BFloat16 Multiply |
| 0x65018000 | bfsub | BFSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE BFloat16 | BFloat16 Subtract |
| 0x0A200000 | bic | BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise Bit Clear (Shifted Register) |
| 0x8A200000 | bic | BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise Bit Clear (Shifted Register 64-bit) |
| 0x0E601C00 | bic | BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Vector Bitwise Bit Clear |
| 0x041B0000 | bic | BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE Bitwise Bit Clear (Predicated) |
| 0x01C00000 | bic | BIC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | Bit Clear (A32) |
| 0xEA200000 | bic.w | BIC.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | Bitwise Bit Clear (Wide) |
| 0x6A200000 | bics | BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Bitwise Bit Clear and Set Flags |
| 0xEA200000 | bics | BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Bitwise Bit Clear and Set Flags (64-bit) |
| 0x2EE01C00 | bif | BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | Bitwise Insert if False |