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ARM Opcode Map

Reverse lookup instructions by their hexadecimal encoding.

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Opcode Mnemonic Syntax Format Name
0x042A0000 abs ABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Integer Unary SVE Absolute Value
0x0E20B800 abs ABS <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Absolute Value
0x1A000000 adc ADC <Wd>, <Wn>, <Wm> Data Processing (3-source) Add with Carry
0x9A000000 adc ADC <Xd>, <Xn>, <Xm> Data Processing (3-source) Add with Carry (64-bit)
0x00A00000 adc ADC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} Data Proc Add with Carry (A32)
0xEB400000 adc.w ADC.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Add with Carry (Wide)
0x3A000000 adcs ADCS <Wd>, <Wn>, <Wm> Data Processing (3-source) Add with Carry and Set Flags
0xBA000000 adcs ADCS <Xd>, <Xn>, <Xm> Data Processing (3-source) Add with Carry and Set Flags (64-bit)
0x0B200000 add ADD <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} Data Processing (Register) Add (Extended Register)
0x8B200000 add ADD <Xd|SP>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} Data Processing (Register) Add (Extended Register 64-bit)
0x11000000 add ADD <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} Data Processing (Immediate) Add (Immediate)
0x91000000 add ADD <Xd|SP>, <Xn|SP>, #<imm> {, lsl #<shift>} Data Processing (Immediate) Add (Immediate 64-bit)
0x0B000000 add ADD <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Data Processing (Register) Add (Shifted Register)
0x8B000000 add ADD <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Data Processing (Register) Add (Shifted Register 64-bit)
0x0E208400 add ADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Add (Integer)
0x04000000 add ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Integer Add (Predicated)
0x00800000 add ADD{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} Data Proc Add (A32)
0xEB000000 add.w ADD.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Add (Wide)
0x91000000 addg ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> Data Processing Add with Tag
0x5EF1B800 addp ADDP <Dd>, <Vn>.<T> NEON Scalar Scalar Add Pairwise
0x0E20BC00 addp ADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Add Pairwise
0x2B200000 adds ADDS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} Data Processing (Register) Add and Set Flags (Extended Register)
0xAB200000 adds ADDS <Xd>, <Xn|SP>, <R><m> {, <extend> {#<amount>}} Data Processing (Register) Add and Set Flags (Extended Register 64-bit)
0x31000000 adds ADDS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} Data Processing (Immediate) Add and Set Flags (Immediate)
0xB1000000 adds ADDS <Xd>, <Xn|SP>, #<imm> {, lsl #<shift>} Data Processing (Immediate) Add and Set Flags (Immediate 64-bit)
0x2B000000 adds ADDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Data Processing (Register) Add and Set Flags (Shifted Register)
0xAB000000 adds ADDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Data Processing (Register) Add and Set Flags (Shifted Register 64-bit)
0x0E31B800 addv ADDV <V><d>, <Vn>.<T> SIMD Across Lane Vector Add Across
0x10000000 adr ADR <Xd>, <label> PC-rel Form PC-relative Address
0xA000 adr ADR <Rd>, <label> Thumb Data Proc Form PC-relative Address (Thumb)
0x028F0000 adr ADR<c> <Rd>, <label> Data Proc Form PC-relative Address (A32)
0xF20F0000 adr.w ADR.W <Rd>, <label> Thumb Data Proc Form PC-relative Address (Wide)
0x90000000 adrp ADRP <Xd>, <label> PC-rel Form PC-relative Address to 4KB Page
0xF3B00380 aesd AESD.8 <Qd>, <Qm> Crypto 2-Reg AES Decrypt (A32)
0x4E285800 aesd AESD <Vd>.16B, <Vm>.16B Crypto AES Decrypt (A64)
0x4E285800 aesd AESD <Vd>.<T>, <Vn>.<T> Crypto AES Decrypt
0xF3B00300 aese AESE.8 <Qd>, <Qm> Crypto 2-Reg AES Encrypt (A32)
0x4E284800 aese AESE <Vd>.16B, <Vm>.16B Crypto AES Encrypt (A64)
0x4E284800 aese AESE <Vd>.<T>, <Vn>.<T> Crypto AES Encrypt
0xF3B20380 aesimc AESIMC.8 <Qd>, <Qm> Crypto 2-Reg AES Inverse Mix Columns (A32)
0x4E287800 aesimc AESIMC <Vd>.<T>, <Vn>.<T> Crypto AES Inverse Mix Columns
0xF3B20300 aesmc AESMC.8 <Qd>, <Qm> Crypto 2-Reg AES Mix Columns (A32)
0x4E286800 aesmc AESMC <Vd>.<T>, <Vn>.<T> Crypto AES Mix Columns
0x12000000 and AND <Wd|Wsp>, <Wn>, #<imm> Logical (Immediate) Bitwise AND (Immediate)
0x92000000 and AND <Xd|SP>, <Xn>, #<imm> Logical (Immediate) Bitwise AND (Immediate 64-bit)
0x0A000000 and AND <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise AND (Shifted Register)
0x8A000000 and AND <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Logical (Register) Bitwise AND (Shifted Register 64-bit)
0x0E201C00 and AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise AND
0x040C0000 and AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Logic SVE Bitwise AND (Predicated)
0x00000000 and AND{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} Data Proc Bitwise AND (A32)
0xEA000000 and.w AND.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise AND (Wide)
0x72000000 ands ANDS <Wd>, <Wn>, #<imm> Logical (Immediate) Bitwise AND and Set Flags (Immediate)
0xF2000000 ands ANDS <Xd>, <Xn>, #<imm> Logical (Immediate) Bitwise AND and Set Flags (Immediate 64-bit)
0x6A000000 ands ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise AND and Set Flags (Shifted Register)
0xEA000000 ands ANDS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Logical (Register) Bitwise AND and Set Flags (Shifted Register 64-bit)
0x04050000 andv ANDV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Bitwise AND Reduction
0x13000000 asr ASR <Wd>, <Wn>, #<shift> Data Processing (Immediate) Arithmetic Shift Right (Immediate)
0x93000000 asr ASR <Xd>, <Xn>, #<shift> Data Processing (Immediate) Arithmetic Shift Right (Immediate 64-bit)
0x1AC02800 asr ASR <Wd>, <Wn>, <Wm> Data Processing (Register) Arithmetic Shift Right (Register)
0x9AC02800 asr ASR <Xd>, <Xn>, <Xm> Data Processing (Register) Arithmetic Shift Right (Register 64-bit)
0x040A0000 asr ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Shift SVE Arithmetic Shift Right (Predicated)
0x01A00050 asr ASR{S}<c> <Rd>, <Rm>, <Rs> Data Proc Arithmetic Shift Right (A32)
0xD5087800 at AT S1E1R, <Xt> System Address Translate (Stage 1 Current)
0xD5087820 at AT S1E1W, <Xt> System Address Translate (Stage 1 Write)
0xD5080000 at AT <op>, <Xt> System Alias Address Translate
0xDAC11800 autda AUTDA <Xd>, <Xn> Data Processing Authenticate Data Address (Key A)
0xDAC11C00 autdb AUTDB <Xd>, <Xn> Data Processing Authenticate Data Address (Key B)
0xDAC503E0 autia AUTIA <Xd>, <Xn|SP> Data Processing Authenticate Code (Inst A)
0xDAC11000 autia AUTIA <Xd>, <Xn> Data Processing Authenticate Instruction Address (Key A)
0xDAC503E0 autib AUTIB <Xd>, <Xn|SP> Data Processing Authenticate Code (Inst B)
0xDAC11400 autib AUTIB <Xd>, <Xn> Data Processing Authenticate Instruction Address (Key B)
0x14000000 b B <label> Branch Branch
0x0A000000 b B<c> <label> Branch Branch (A32)
0x54000000 b.cond B.cond <label> Branch Branch Conditional
0xF0009000 b.w B.W <label> Thumb Branch Branch (Wide)
0x54000010 bc.cond BC.cond <label> Branch Branch Consistent Conditional
0x65000000 bfadd BFADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE BFloat16 BFloat16 Add
0xF36F0000 bfc BFC <Rd>, #<lsb>, #<width> Thumb Bitfield Bit Field Clear (Thumb)
0x07C0001F bfc BFC<c> <Rd>, #<lsb>, #<width> Data Proc Bit Field Clear
0x1E218800 bfcvtn BFCVTN <Vd>.<Tb>, <Vn>.<Ta> NEON 2-Reg BFloat16 Convert Narrow (NEON)
0x5E218800 bfcvtn2 BFCVTN2 <Vd>.<Tb>, <Vn>.<Ta> NEON 2-Reg BFloat16 Convert Narrow High (NEON)
0x4E40FC00 bfdot BFDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg BFloat16 Dot Product (NEON)
0xF3600000 bfi BFI <Rd>, <Rn>, #<lsb>, #<width> Thumb Bitfield Bit Field Insert (Thumb)
0x07C00010 bfi BFI<c> <Rd>, <Rn>, #<lsb>, #<width> Data Proc Bit Field Insert
0x33000000 bfm BFM <Wd>, <Wn>, #<immr>, #<imms> Bitfield Bitfield Move
0xB3400000 bfm BFM <Xd>, <Xn>, #<immr>, #<imms> Bitfield Bitfield Move (64-bit)
0x65008000 bfmax BFMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE BFloat16 BFloat16 Maximum
0x6500A000 bfmin BFMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE BFloat16 BFloat16 Minimum
0x4E60FC00 bfmmla BFMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg BFloat16 Matrix Multiply-Accumulate (NEON)
0x65004000 bfmul BFMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE BFloat16 BFloat16 Multiply
0x65002000 bfsub BFSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE BFloat16 BFloat16 Subtract
0x0A200000 bic BIC <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise Bit Clear (Shifted Register)
0x8A200000 bic BIC <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Logical (Register) Bitwise Bit Clear (Shifted Register 64-bit)
0x0E601C00 bic BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise Bit Clear
0x040F0000 bic BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Logic SVE Bitwise Bit Clear (Predicated)
0x01C00000 bic BIC{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} Data Proc Bit Clear (A32)
0xEA200000 bic.w BIC.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise Bit Clear (Wide)
0x6A200000 bics BICS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise Bit Clear and Set Flags
0xEA200000 bics BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Logical (Register) Bitwise Bit Clear and Set Flags (64-bit)
0x2EE01C00 bif BIF <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Bitwise Insert if False
0x2EA01C00 bit BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Bitwise Insert if True
0xBE00 bkpt BKPT #<imm> Thumb System Breakpoint (Thumb)
0xE1200070 bkpt BKPT #<imm> System Breakpoint (A32)
0x94000000 bl BL <label> Branch Branch with Link
0x0B000000 bl BL<c> <label> Branch Branch with Link (A32)
0xF000D000 bl.w BL.W <label> Thumb Branch Branch with Link (Wide)
0xD63F0000 blr BLR <Xn> Branch (Reg) Branch with Link to Register
0x012FFF30 blx BLX<c> <Rm> Branch Branch with Link and Exchange
0xD61F0000 br BR <Xn> Branch (Reg) Branch to Register
0xD503201F brb BRB <op> System Branch Record Buffer Injection
0xD503225F brbtsy BRBTSY System Branch Record Buffer Timestamp Synchronize
0xD4200000 brk BRK #<imm> Exception Breakpoint
0x25400000 brka BRKA <Pd>.B, <Pg>/Z, <Pn>.B SVE Predicate SVE Break After First True
0x25410000 brkb BRKB <Pd>.B, <Pg>/Z, <Pn>.B SVE Predicate SVE Break Before First True
0x2E601C00 bsl BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Bitwise Select
0xD503241F bti BTI <target> System Hint Branch Target Identification
0xD503241F bti BTI {<target>} System Branch Target Identification
0x012FFF10 bx BX<c> <Rm> Branch Branch and Exchange
0x012FFF20 bxj BXJ<c> <Rm> Branch Branch and Exchange Jazelle (A32)
0x88A07C00 cas CAS <Ws>, <Wt>, [<Xn|SP>] Atomic Compare and Swap Word
0xC8A07C00 cas CAS <Xs>, <Xt>, [<Xn|SP>] Atomic Compare and Swap Doubleword
0x88E07C00 casa CASA <Ws>, <Wt>, [<Xn|SP>] Atomic Compare and Swap Word (Acquire)
0x88E0FC00 casal CASAL <Ws>, <Wt>, [<Xn|SP>] Atomic Compare and Swap Word (Acquire-Release)
0x88A0FC00 casl CASL <Ws>, <Wt>, [<Xn|SP>] Atomic Compare and Swap Word (Release)
0x48207C00 casp CASP <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>] Atomic Compare and Swap Pair
0x35000000 cbnz CBNZ <Wt>, <label> Branch Compare and Branch Not Zero
0xB5000000 cbnz CBNZ <Xt>, <label> Branch Compare and Branch Not Zero (64-bit)
0xB900 cbnz CBNZ <Rn>, <label> Thumb Branch Compare and Branch Non-Zero (Thumb)
0x34000000 cbz CBZ <Wt>, <label> Branch Compare and Branch Zero
0xB4000000 cbz CBZ <Xt>, <label> Branch Compare and Branch Zero (64-bit)
0xB100 cbz CBZ <Rn>, <label> Thumb Branch Compare and Branch Zero (Thumb)
0x3A400800 ccmn CCMN <Wn>, #<imm>, #<nzcv>, <cond> Cond Comp Conditional Compare Negative (Immediate)
0xBA400800 ccmn CCMN <Xn>, #<imm>, #<nzcv>, <cond> Cond Comp Conditional Compare Negative (Immediate 64-bit)
0x3A400000 ccmn CCMN <Wn>, <Wm>, #<nzcv>, <cond> Cond Comp Conditional Compare Negative (Register)
0x7A400800 ccmp CCMP <Wn>, #<imm>, #<nzcv>, <cond> Cond Comp Conditional Compare (Immediate)
0x7A400000 ccmp CCMP <Wn>, <Wm>, #<nzcv>, <cond> Cond Comp Conditional Compare (Register)
0x0E000000 cdp CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> Coprocessor Coprocessor Data Processing (A32)
0xFE000000 cdp2 CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> Coprocessor Coprocessor Data Processing 2 (A32)
0xD500401F cfinv CFINV System Condition Flag Invert
0xD5032040 chk CHK <#imm> System Check
0x1A800400 cinc CINC <Wd>, <Wn>, <cond> Cond Select Conditional Increment
0x5A800000 cinv CINV <Wd>, <Wn>, <cond> Cond Select Conditional Invert
0x05A00000 clasta CLASTA <Rdn>, <Pg>, <Rdn>, <Zm>.<T> SVE Extract SVE Conditional Last Element After
0x05A08000 clastb CLASTB <Rdn>, <Pg>, <Rdn>, <Zm>.<T> SVE Extract SVE Conditional Last Element Before
0xF3BF8F2F clrex CLREX Thumb System Clear Exclusive (Thumb)
0xD503305F clrex CLREX {#<imm>} System Clear Exclusive (System)
0xF57FF01F clrex CLREX<c> System Clear Exclusive (A32)
0x5AC01400 cls CLS <Wd>, <Wn> Data Processing Count Leading Sign Bits
0x5AC01000 clz CLZ <Wd>, <Wn> Data Processing Count Leading Zeros
0xFAB0F080 clz CLZ <Rd>, <Rm> Thumb Misc Count Leading Zeros (Thumb)
0x016F0F10 clz CLZ<c> <Rd>, <Rm> Data Proc Count Leading Zeros (A32)
0x2E204800 clz CLZ <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Count Leading Zeros
0x2E208C00 cmeq CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Compare Equal
0x0E203C00 cmge CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Compare Greater Than or Equal
0x0E203400 cmgt CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Compare Greater Than
0x3100001F cmn CMN <Wn>, #<imm> Data Processing Compare Negative (Immediate)
0x01700000 cmn CMN<c> <Rn>, <Rm> {, <shift>} Data Proc Compare Negative (A32)
0xEB100F00 cmn.w CMN.W <Rn>, <Operand2> Thumb2 Data Proc Compare Negative (Wide)
0x7100001F cmp CMP <Wn>, #<imm> Data Processing Compare (Immediate)
0x01500000 cmp CMP<c> <Rn>, <Rm> {, <shift>} Data Proc Compare (A32)
0xEBB00F00 cmp.w CMP.W <Rn>, <Operand2> Thumb2 Data Proc Compare (Wide)
0x24000000 cmpeq CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> SVE Compare SVE Compare Equal (Integer)
0x24030000 cmpgt CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> SVE Compare SVE Compare Greater Than (Signed)
0x0E208C00 cmtst CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Compare Test
0x4A800400 cneg CNEG <Wd>, <Wn>, <cond> Cond Select Conditional Negate
0x0E205800 cnt CNT <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Population Count
0x25200000 cntp CNTP <Xn>, <Pg>, <Pn>.<T> SVE Count SVE Count Active Predicates
0x05610000 compact COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> SVE Permute SVE Compact Vector
0xD5033420 cosp COSP <Xt> System Call Out Speculation
0xD503321F cosp COSP <Xt> System Call Out Speculation
0xD5033440 cppp CPPP <Xt> System Cache Prefetch Prediction Pruning
0xF1000000 cps CPS<effect> <iflags> {, #<mode>} System Change Processor State
0xB660 cps CPS<effect> <iflags> {, #<mode>} Thumb System Change Processor State (Thumb)
0x05201000 cpy CPY <Zd>.<T>, <Pg>/M, <R><n> SVE Move SVE Copy (Predicated)
0x05210000 cpy CPY <Zd>.<T>, <Pg>/M, <Zn>.<T> SVE2 Move Memory Copy (SVE2)
0x01000040 crc32b CRC32B<c> <Rd>, <Rn>, <Rm> Data Proc CRC32 Byte (A32)
0x1AC04000 crc32b CRC32B <Wd>, <Wn>, <Wm> Data Processing CRC32 Byte
0x1AC05000 crc32cb CRC32CB <Wd>, <Wn>, <Wm> Data Processing CRC32C Byte
0x01200040 crc32w CRC32W<c> <Rd>, <Rn>, <Rm> Data Proc CRC32 Word (A32)
0x1AC04800 crc32w CRC32W <Wd>, <Wn>, <Wm> Data Processing CRC32 Word
0x9AC04C00 crc32x CRC32X <Wd>, <Wn>, <Xm> Data Processing CRC32 Doubleword
0x0320F014 csdb CSDB System Hint Consumption of Speculative Data Barrier (A32)
0xF57FF050 csdb CSDB System Hint Consumption of Speculative Data Barrier (A32)
0xD503229F csdb CSDB System Hint Consumption of Speculative Data Barrier
0x1A800000 csel CSEL <Wd>, <Wn>, <Wm>, <cond> Cond Select Conditional Select
0x1A9F07E0 cset CSET <Wd>, <cond> Cond Select Conditional Set
0x1A800400 csinc CSINC <Wd>, <Wn>, <Wm>, <cond> Cond Select Conditional Select Increment
0x5A800000 csinv CSINV <Wd>, <Wn>, <Wm>, <cond> Cond Select Conditional Select Invert
0x4A800400 csneg CSNEG <Wd>, <Wn>, <Wm>, <cond> Cond Select Conditional Select Negate
0x0320F0F0 dbg DBG #<option> System Hint Debug Hint
0x3AA0 dbg DBG #<option> Thumb System Debug Hint (Thumb)
0xD5080000 dc DC <op>, <Xt> System Alias Data Cache Operation
0xF4A00001 dcps1 DCPS1 System Debug Change PE State to EL1 (A32)
0xD4A00001 dcps1 DCPS1 {#<imm>} Exception Debug Change PE State to EL1
0xF4A00002 dcps2 DCPS2 System Debug Change PE State to EL2 (A32)
0xD4A00002 dcps2 DCPS2 {#<imm>} Exception Debug Change PE State to EL2
0xF4A00003 dcps3 DCPS3 System Debug Change PE State to EL3 (A32)
0xD4A00003 dcps3 DCPS3 {#<imm>} Exception Debug Change PE State to EL3
0x04310000 decb DECB <Xdn>, <pattern> {, MUL #<imm>} SVE Inc/Dec SVE Decrement Scalar by Byte Count
0x04F10000 decd DECD <Xdn>, <pattern> {, MUL #<imm>} SVE Inc/Dec SVE Decrement Scalar by Doubleword Count
0x04B10000 decw DECW <Xdn>, <pattern> {, MUL #<imm>} SVE Inc/Dec SVE Decrement Scalar by Word Count
0xF57FF04C dfb DFB System Hint Debug Flush Barrier (A32)
0xD50320DF dgh DGH System Hint Data Gathering Hint
0xD50330BF dmb DMB <option> System Data Memory Barrier
0xF3BF8F50 dmb DMB <option> Thumb System Data Memory Barrier (Thumb)
0xF57FF050 dmb DMB <option> System Data Memory Barrier (A32)
0xD6BF03E0 drps DRPS System Debug Restore PE State
0xD503309F dsb DSB <option> System Data Synchronization Barrier
0xF3BF8F40 dsb DSB <option> Thumb System Data Synchronization Barrier (Thumb)
0xF57FF040 dsb DSB <option> System Data Synchronization Barrier (A32)
0x0E000400 dup DUP <Vd>.<T>, <R><n> SIMD Copy Duplicate Vector Element (Scalar)
0x0E000400 dup DUP <Vd>.<T>, <Vn>.<Ts>[<index>] SIMD Copy Duplicate Vector Element (Element)
0x05203000 dup DUP <Zd>.<T>, <R><n|m> SVE Move SVE Duplicate Scalar
0x4A000000 eon EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise Exclusive OR NOT
0xCA000000 eon EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>} Logical (Register) Bitwise Exclusive OR NOT (64-bit)
0x52000000 eor EOR <Wd|Wsp>, <Wn>, #<imm> Logical (Immediate) Bitwise Exclusive OR (Immediate)
0x4A000000 eor EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise Exclusive OR (Register)
0x2E201C00 eor EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise Exclusive OR
0x040E0000 eor EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Logic SVE Bitwise Exclusive OR (Predicated)
0x00200000 eor EOR{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} Data Proc Exclusive OR (A32)
0xEA800000 eor.w EOR.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise Exclusive OR (Wide)
0x04070000 eorv EORV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Bitwise EOR Reduction
0xD69F03E0 eret ERET System Exception Return
0xF800000E eret ERET System Exception Return (A32)
0xF3DE8F00 eret ERET Thumb System Exception Return (Thumb)
0x0320F010 esb ESB System Hint Error Synchronization Barrier (A32)
0xD503221F esb ESB System Alias Error Synchronization Barrier
0xF57FF050 esb ESB System Hint Error Synchronization Barrier (A32)
0x05250000 ext EXT <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm> SVE Permute SVE Extract Vector
0x2E000000 ext EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> SIMD Extract Extract Vector
0x13800000 extr EXTR <Wd>, <Wn>, <Wm>, #<lsb> Data Processing Extract
0x93C00000 extr EXTR <Xd>, <Xn>, <Xm>, #<lsb> Data Processing Extract (64-bit)
0x65280000 fabs FABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE FP Unary SVE Floating-Point Absolute Value
0x1E20C000 fabs FABS <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Absolute Value (Scalar)
0x0EA0F800 fabs FABS <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Floating-Point Absolute Value
0x4EF87800 fabs FABS <Vd>.8H, <Vn>.8H NEON FP16 Floating-Point Absolute Value (Half-Precision)
0x1E202800 fadd FADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Add (Scalar)
0x0E20D400 fadd FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Add
0x65000000 fadd FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE FP Binary SVE Floating-Point Add
0x4E20D400 fadd FADD <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Add (Half-Precision)
0x1E202800 fadd FADD <Sd>, <Sn>, <Sm> Float Data Proc Floating-point Add (Single)
0x1E602800 fadd FADD <Dd>, <Dn>, <Dm> Float Data Proc Floating-point Add (Double)
0x2E20D400 faddp FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Add Pairwise
0x65200000 faddv FADDV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Floating-Point Add Reduction
0x64000000 fcadd FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, #<rot> SVE FP Complex SVE Floating-Point Complex Add
0x6E40E400 fcadd FCADD <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> NEON Complex Floating-Point Complex Add (NEON)
0x1E200400 fccmp FCCMP <Hn|Sn|Dn>, <Hm|Sm|Dm>, #<nzcv>, <cond> FP Compare Floating-Point Conditional Compare (Scalar)
0x64200000 fcmla FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, #<rot> SVE FP Complex SVE Floating-Point Complex Multiply-Add
0x4E40E400 fcmla FCMLA <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> NEON Complex Floating-Point Complex Multiply Accumulate (NEON)
0x1E202000 fcmp FCMP <Hn|Sn|Dn>, <Hm|Sm|Dm|#0.0> FP Compare Floating-Point Compare (Scalar)
0x1E202000 fcmp FCMP <Sn>, <Sm> Float Compare Floating-point Compare (Single)
0x1E602000 fcmp FCMP <Dn>, <Dm> Float Compare Floating-point Compare (Double)
0x64000000 fcmpeq FCMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> SVE FP Compare SVE Floating-Point Compare Equal
0x64030000 fcmpgt FCMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> SVE FP Compare SVE Floating-Point Compare Greater Than
0x1E200C00 fcsel FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond> FP Data Processing Floating-Point Conditional Select (Scalar)
0x1E220000 fcvt FCVT <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert (Scalar)
0x1E200000 fcvtas FCVTAS <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Signed Integer (Nearest)
0x1E210000 fcvtau FCVTAU <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Unsigned Integer (Nearest)
0x4E217800 fcvtl FCVTL <Vd>.4S, <Vn>.4H NEON FP16 Floating-Point Convert Long (Half to Single)
0x0E20B800 fcvtl FCVTL <Vd>.<Td>, <Vn>.<Ts> SIMD Two Register Vector Floating-Point Convert Long
0x6E217800 fcvtl2 FCVTL2 <Vd>.4S, <Vn>.8H NEON FP16 Floating-Point Convert Long High (Half to Single)
0x1E300000 fcvtms FCVTMS <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Signed Integer (Minus Infinity)
0x1E310000 fcvtmu FCVTMU <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Unsigned Integer (Minus Infinity)
0x4E216800 fcvtn FCVTN <Vd>.4H, <Vn>.4S NEON FP16 Floating-Point Convert Narrow (Single to Half)
0x0E20B000 fcvtn FCVTN <Vd>.<Td>, <Vn>.<Ts> SIMD Two Register Vector Floating-Point Convert Narrow
0x6E216800 fcvtn2 FCVTN2 <Vd>.8H, <Vn>.4S NEON FP16 Floating-Point Convert Narrow High (Single to Half)
0x1E200000 fcvtns FCVTNS <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Signed Integer (Nearest, ties to Even)
0x1E210000 fcvtnu FCVTNU <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Unsigned Integer (Nearest, ties to Even)
0x1E280000 fcvtps FCVTPS <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Signed Integer (Plus Infinity)
0x1E290000 fcvtpu FCVTPU <Wd|Xd>, <Hn|Sn|Dn> FP Conversion Floating-Point Convert to Unsigned Integer (Plus Infinity)
0x655A0000 fcvtzs FCVTZS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Conversion SVE Floating-Point Convert to Signed Integer
0x1E380000 fcvtzs FCVTZS <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} FP Conversion Floating-Point Convert to Signed Integer (Zero)
0x9E380000 fcvtzs FCVTZS <Xd>, <Dn> Float Conversion Floating-point Convert to Signed Integer (Round towards Zero)
0x0E20D800 fcvtzs FCVTZS <Vd>.<T>, <Vn>.<T> {, #<fbits>} SIMD Two Register Vector Floating-Point Convert to Signed Integer
0x655B0000 fcvtzu FCVTZU <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Conversion SVE Floating-Point Convert to Unsigned Integer
0x1E390000 fcvtzu FCVTZU <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} FP Conversion Floating-Point Convert to Unsigned Integer (Zero)
0x2E20D800 fcvtzu FCVTZU <Vd>.<T>, <Vn>.<T> {, #<fbits>} SIMD Two Register Vector Floating-Point Convert to Unsigned Integer
0x1E201800 fdiv FDIV <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Divide (Scalar)
0x2E20FC00 fdiv FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Divide
0x6500C000 fdiv FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE FP Binary SVE Floating-Point Divide
0x6EA0D400 fdiv FDIV <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Divide (Half-Precision)
0x1E201800 fdiv FDIV <Sd>, <Sn>, <Sm> Float Data Proc Floating-point Divide (Single)
0x1E601800 fdiv FDIV <Dd>, <Dn>, <Dm> Float Data Proc Floating-point Divide (Double)
0x1E7E0000 fjcvtzs FJCVTZS <Wd>, <Dn> Float Convert Floating-Point Javascript Convert
0x1F000000 fmadd FMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> FP Data Processing Floating-Point Fused Multiply-Add (Scalar)
0x1E204800 fmax FMAX <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Maximum (Scalar)
0x0E20F400 fmax FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Maximum
0x65008000 fmax FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE FP Binary SVE Floating-Point Maximum
0x4E20F400 fmax FMAX <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Maximum (Half-Precision)
0x1E206800 fmaxnm FMAXNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Max Number (Scalar)
0x2E20F400 fmaxp FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Max Pairwise
0x65010000 fmaxv FMAXV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Floating-Point Maximum Reduction
0x6E30F800 fmaxv FMAXV <Sd>, <Vn>.<T> NEON Reduction Floating-Point Maximum Reduction (NEON)
0x1E205800 fmin FMIN <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Minimum (Scalar)
0x0EA0F400 fmin FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Minimum
0x6500A000 fmin FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE FP Binary SVE Floating-Point Minimum
0x4EA0F400 fmin FMIN <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Minimum (Half-Precision)
0x1E207800 fminnm FMINNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Min Number (Scalar)
0x2EA0F400 fminp FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Min Pairwise
0x65020000 fminv FMINV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Floating-Point Minimum Reduction
0x6EB0F800 fminv FMINV <Sd>, <Vn>.<T> NEON Reduction Floating-Point Minimum Reduction (NEON)
0x0E20CC00 fmla FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Multiply-Accumulate
0x65200000 fmla FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> SVE FP Ternary SVE Floating-Point Fused Multiply-Add
0x4E20CC00 fmla FMLA <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Multiply Accumulate (Half-Precision)
0x0EA0CC00 fmls FMLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Multiply-Subtract
0x65202000 fmls FMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> SVE FP Ternary SVE Floating-Point Fused Multiply-Subtract
0x4EA0CC00 fmls FMLS <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Multiply Subtract (Half-Precision)
0x1E201000 fmov FMOV <Hd|Sd|Dd>, #<fimm> FP Immediate Floating-Point Move (Immediate)
0x1E204000 fmov FMOV <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Move (Register)
0x1E260000 fmov FMOV <Wd|Xd>, <Sn|Dn> FP Conversion Floating-Point Move (General)
0x1E270000 fmov FMOV <Sd|Dd>, <Wn|Xn> FP Conversion Floating-Point Move (General to FP)
0x1E604000 fmov FMOV <Dd>, <Dn> Float Data Proc Floating-point Move (Register)
0x1E601000 fmov FMOV <Dd>, #<imm> Float Imm Floating-point Move (Immediate)
0x1F008000 fmsub FMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> FP Data Processing Floating-Point Fused Multiply-Subtract (Scalar)
0x1E200800 fmul FMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Multiply (Scalar)
0x2E20DC00 fmul FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Multiply
0x65004000 fmul FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE FP Binary SVE Floating-Point Multiply
0x6E20D400 fmul FMUL <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Multiply (Half-Precision)
0x1E200800 fmul FMUL <Sd>, <Sn>, <Sm> Float Data Proc Floating-point Multiply (Single)
0x1E600800 fmul FMUL <Dd>, <Dn>, <Dm> Float Data Proc Floating-point Multiply (Double)
0x65290000 fneg FNEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE FP Unary SVE Floating-Point Negate
0x1E204000 fneg FNEG <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Negate (Scalar)
0x2EA0F800 fneg FNEG <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Floating-Point Negate
0x6EF87800 fneg FNEG <Vd>.8H, <Vn>.8H NEON FP16 Floating-Point Negate (Half-Precision)
0x1F200000 fnmadd FNMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> FP Data Processing Floating-Point Fused Negated Multiply-Add (Scalar)
0x1F208000 fnmsub FNMSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> FP Data Processing Floating-Point Fused Negated Multiply-Subtract (Scalar)
0x1E208800 fnmul FNMUL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Negated Multiply (Scalar)
0x2EA0E800 frecpe FRECPE <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Floating-Point Reciprocal Estimate
0x0E20FC00 frecps FRECPS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Reciprocal Step
0x1E28E000 frint32x FRINT32X <Sd>, <Sn> Float Conversion Floating-Point Round to 32-bit Integer (Exact)
0x1E29E000 frint32z FRINT32Z <Sd>, <Sn> Float Conversion Floating-Point Round to 32-bit Integer (Zero)
0x1E2AE000 frint64x FRINT64X <Sd>, <Sn> Float Conversion Floating-Point Round to 64-bit Integer (Exact)
0x1E2BE000 frint64z FRINT64Z <Sd>, <Sn> Float Conversion Floating-Point Round to 64-bit Integer (Zero)
0x1E264000 frinta FRINTA <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Nearest)
0x1E27C000 frinti FRINTI <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Current)
0x1E254000 frintm FRINTM <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Minus Infinity)
0x1E244000 frintn FRINTN <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Nearest Even)
0x1E24C000 frintp FRINTP <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Plus Infinity)
0x1E274000 frintx FRINTX <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Exact)
0x1E25C000 frintz FRINTZ <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Round to Integral (Zero)
0x2EA0F800 frsqrte FRSQRTE <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Floating-Point Reciprocal Sqrt Estimate
0x0EA0FC00 frsqrts FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Reciprocal Sqrt Step
0x652A0000 fsqrt FSQRT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE FP Unary SVE Floating-Point Square Root
0x1E21C000 fsqrt FSQRT <Hd|Sd|Dd>, <Hn|Sn|Dn> FP Data Processing Floating-Point Square Root (Scalar)
0x2EA1F800 fsqrt FSQRT <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Floating-Point Square Root
0x7EF87800 fsqrt FSQRT <Vd>.8H, <Vn>.8H NEON FP16 Floating-Point Square Root (Half-Precision)
0x1E203800 fsub FSUB <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> FP Data Processing Floating-Point Subtract (Scalar)
0x0E20D400 fsub FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Floating-Point Subtract
0x65002000 fsub FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE FP Binary SVE Floating-Point Subtract
0x4EA0D400 fsub FSUB <Vd>.8H, <Vn>.8H, <Vm>.8H NEON FP16 Floating-Point Subtract (Half-Precision)
0x1E203800 fsub FSUB <Sd>, <Sn>, <Sm> Float Data Proc Floating-point Subtract (Single)
0x1E603800 fsub FSUB <Dd>, <Dn>, <Dm> Float Data Proc Floating-point Subtract (Double)
0xD52B245F gcspopm GCSPOPM System Guarded Control Stack Pop
0xD52B2700 gcsss1 GCSSS1 <Xt> System Guarded Control Stack Switch Stack 1
0xD52B2720 gcsss2 GCSSS2 <Xt> System Guarded Control Stack Switch Stack 2
0x9AC01400 gmi GMI <Xd>, <Xn|SP>, <Xm> Data Processing Get Memory Tag Intersection
0xD503201F hint HINT #<imm> System Hint
0xD4400000 hlt HLT #<imm> Exception Halting Debug-mode
0xBA80 hlt HLT #<imm> Thumb System Halting Debug (Thumb)
0x01000070 hlt HLT #<imm> System Halting Debug (A32)
0xD4000002 hvc HVC #<imm> Exception Hypervisor Call
0xF7E08000 hvc HVC #<imm> Thumb System Hypervisor Call (Thumb)
0x01400070 hvc HVC #<imm> System Hypervisor Call (A32)
0xD5080000 ic IC <op> {, <Xt>} System Alias Instruction Cache Operation
0x04300000 incb INCB <Xdn>, <pattern> {, MUL #<imm>} SVE Inc/Dec SVE Increment Scalar by Byte Count
0x04F00000 incd INCD <Xdn>, <pattern> {, MUL #<imm>} SVE Inc/Dec SVE Increment Scalar by Doubleword Count
0x04B00000 incw INCW <Xdn>, <pattern> {, MUL #<imm>} SVE Inc/Dec SVE Increment Scalar by Word Count
0x04400000 index INDEX <Zd>.<T>, <Start>, <Step> SVE Index SVE Create Index Vector
0x4E001C00 ins INS <Vd>.<Ts>[<index>], <Rn> SIMD Copy Insert Vector Element (General)
0x0520C000 insr INSR <Zdn>.<T>, <R><m> SVE Move SVE Insert Scalar
0x9AC01000 irg IRG <Xd|SP>, <Xn|SP>{, <Xm>} Data Processing Insert Random Tag
0x9AC01000 irg IRG <Xd|SP>, <Xn|SP> {, <Xm>} Data Processing Insert Random Tag
0xD50330DF isb ISB {<option>} System Instruction Synchronization Barrier
0xF3BF8F60 isb ISB <option> Thumb System Instruction Synchronization Barrier (Thumb)
0xF57FF060 isb ISB <option> System Instruction Synchronization Barrier (A32)
0xBF00 it IT{x{y{z}}} <cond> Thumb IT If-Then (Thumb)
0x05800000 lasta LASTA <Vd>.<T>, <Pg>, <Zn>.<T> SVE Extract SVE Extract Last Element After
0x05808000 lastb LASTB <Vd>.<T>, <Pg>, <Zn>.<T> SVE Extract SVE Extract Last Element Before
0x0D400000 ld1 LD1 { <Vt>.<T>, ... }, [<Xn|SP>] SIMD Load/Store Load Multiple Single Elements
0xA4000000 ld1b LD1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Contiguous Bytes
0xA4C00000 ld1d LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Contiguous Doublewords
0xA4400000 ld1h LD1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Contiguous Halfwords
0x0D40C000 ld1r LD1R { <Vt>.<T> }, [<Xn|SP>] SIMD Load/Store Load Single Element Replicate
0xA4800000 ld1w LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Contiguous Words
0x84800000 ld1w LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, SXTW #<shift>] SVE Gather SVE Gather Load Words (Vector Index)
0x0C400000 ld2 LD2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Load Multiple 2-Element Structures
0x0D60C000 ld2r LD2R { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Load 2-Element Structure Replicate
0x0C402000 ld3 LD3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] SIMD Load/Store Load Multiple 3-Element Structures
0x0C404000 ld4 LD4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] SIMD Load/Store Load Multiple 4-Element Structures
0xF81F7C00 ld64b LD64B <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Load
0x01900F9F lda LDA<c> <Rt>, [<Rn>] Load/Store Load Acquire (A32)
0xB8200000 ldadd LDADD <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Add Word
0x01D00F9F ldaexb LDAEXB<c> <Rt>, [<Rn>] Load Excl Load Acquire Exclusive Byte (A32)
0x01B00F9F ldaexd LDAEXD<c> <Rt>, <Rt2>, [<Rn>] Load Excl Load Acquire Exclusive Double (A32)
0x01F00F9F ldaexh LDAEXH<c> <Rt>, [<Rn>] Load Excl Load Acquire Exclusive Halfword (A32)
0x01900F9F ldalex LDAEX<c> <Rt>, [<Rn>] Load/Store Load Acquire Exclusive (A32)
0xB8BF C?? ldapr LDAPR <Wt>, [<Xn|SP>] Load/Store Load-Acquire RCpc Register
0x38BF C?? ldaprb LDAPRB <Wt>, [<Xn|SP>] Load/Store Load-Acquire RCpc Register Byte
0x78BF C?? ldaprh LDAPRH <Wt>, [<Xn|SP>] Load/Store Load-Acquire RCpc Register Halfword
0x08BF F?? ldar LDAR <Wt>, [<Xn|SP>] Load/Store Load-Acquire Register
0x08DF F?? ldarb LDARB <Wt>, [<Xn|SP>] Load/Store Load-Acquire Register Byte
0x48DF F?? ldarh LDARH <Wt>, [<Xn|SP>] Load/Store Load-Acquire Register Halfword
0x085F F?? ldaxr LDAXR <Wt>, [<Xn|SP>] Load/Store Excl Load-Acquire Exclusive Register
0x085F F?? ldaxrb LDAXRB <Wt>, [<Xn|SP>] Load/Store Excl Load-Acquire Exclusive Register Byte
0x485F F?? ldaxrh LDAXRH <Wt>, [<Xn|SP>] Load/Store Excl Load-Acquire Exclusive Register Halfword
0x0C100000 ldc LDC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Load Coprocessor (A32)
0xFD100000 ldc2 LDC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Load Coprocessor 2 (A32)
0xB8201000 ldclr LDCLR <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Clear Word
0xB8202000 ldeor LDEOR <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Exclusive OR Word
0xA4200000 ldff1b LDFF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Bytes
0xA4E00000 ldff1d LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Doublewords
0xA4600000 ldff1h LDFF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Halfwords
0xA4A00000 ldff1w LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load First-Fault Contiguous Words
0xD9200000 ldg LDG <Xt>, [<Xn|SP>, #<simm>] Load/Store Load Allocation Tag
0xC800 ldm LDM <Rn>!, <registers> Thumb Load Multiple Load Multiple (Thumb)
0x08800000 ldm LDM<mode><c> <Rn>{!}, <registers> Load Multiple Load Multiple (A32)
0xE8900000 ldm.w LDM.W <Rn>{!}, <registers> Thumb Load Multiple Load Multiple (Wide)
0xA4280000 ldnf1b LDNF1B { <Zt>.B }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Bytes
0xA4E80000 ldnf1d LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Doublewords
0xA4680000 ldnf1h LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Halfwords
0xA4A80000 ldnf1w LDNF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>] SVE Load SVE Load Non-Fault Contiguous Words
0x28400000 ldnp LDNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Load Pair of Registers (Non-temporal)
0x2D400000 ldp LDP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] Load/Store Pair Load Pair SIMD&FP Registers
0x29400000 ldp LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm> Load/Store Pair Load Pair of Registers
0xA9400000 ldp LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm> Load/Store Pair Load Pair of Registers (64-bit)
0x69400000 ldpsw LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] Load/Store Pair Load Pair of Registers Signed Word
0xBD400000 ldr LDR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] Load/Store Load SIMD&FP Register (Immediate)
0xB9400000 ldr LDR <Wt>, [<Xn|SP>, #<pimm>] Load/Store Imm Load Register (Immediate)
0x18000000 ldr LDR <Wt>, <label> Load Literal Load Register (Literal)
0xB8600800 ldr LDR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Load Register (Register)
0x051F0000 ldr LDR<c> <Rt>, <label> Load Literal Load Register PC-Relative (A32)
0x4800 ldr LDR <Rt>, <label> Thumb Load Load Register PC-Relative (Thumb)
0x04000000 ldr LDR<c> <Rt>, [<Rn>, #+/-<imm>]{!} Load/Store Load Register (A32 Immediate)
0xF8D00000 ldr.w LDR.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register (Wide)
0xF8200400 ldraa LDRAA <Xt>, [<Xn|SP>, #<simm>] Load/Store Load Register Authenticate (Key A)
0xF8200C00 ldrab LDRAB <Xt>, [<Xn|SP>, #<simm>] Load/Store Load Register Authenticate (Key B)
0x39400000 ldrb LDRB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Byte (Immediate)
0x38600800 ldrb LDRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Load Register Byte (Register)
0x04400000 ldrb LDRB<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Byte (A32)
0xF8900000 ldrb.w LDRB.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Byte (Wide)
0x04600000 ldrbt LDRBT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Byte Unprivileged
0xE9D00000 ldrd LDRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] Thumb Load Load Register Dual (Thumb)
0x004000D0 ldrd LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>] Load/Store Load Register Dual (A32)
0xE8500F00 ldrex LDREX <Rt>, [<Rn>] Thumb Load Excl Load Register Exclusive (Thumb)
0x01900F9F ldrex LDREX<c> <Rt>, [<Rn>] Load/Store Load Register Exclusive (A32)
0x01D00F9F ldrexb LDREXB<c> <Rt>, [<Rn>] Load/Store Excl Load Register Exclusive Byte (A32)
0xE8D00F4F ldrexb LDREXB <Rt>, [<Rn>] Thumb Load Excl Load Register Exclusive Byte (Thumb)
0x01B00F9F ldrexd LDREXD<c> <Rt>, <Rt2>, [<Rn>] Load/Store Excl Load Register Exclusive Double (A32)
0x01F00F9F ldrexh LDREXH<c> <Rt>, [<Rn>] Load/Store Excl Load Register Exclusive Halfword (A32)
0xE8D00F5F ldrexh LDREXH <Rt>, [<Rn>] Thumb Load Excl Load Register Exclusive Halfword (Thumb)
0x79400000 ldrh LDRH <Wt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Halfword (Immediate)
0x78600800 ldrh LDRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Load Register Halfword (Register)
0x004000B0 ldrh LDRH<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Halfword (A32)
0xF8B00000 ldrh.w LDRH.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Halfword (Wide)
0x002000B0 ldrht LDRHT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Halfword Unprivileged
0x39C00000 ldrsb LDRSB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Signed Byte (Immediate)
0x39800000 ldrsb LDRSB <Xt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Signed Byte (64-bit Immediate)
0x004000D0 ldrsb LDRSB<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Byte (A32)
0xF9900000 ldrsb.w LDRSB.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Signed Byte (Wide)
0x002000D0 ldrsbt LDRSBT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Byte Unprivileged
0x004000F0 ldrsh LDRSH<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Halfword (A32)
0xF9B00000 ldrsh.w LDRSH.W <Rt>, [<Rn>, #<imm>] Thumb Load Load Register Signed Halfword (Wide)
0x002000F0 ldrsht LDRSHT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Signed Halfword Unprivileged
0xB9800000 ldrsw LDRSW <Xt>, [<Xn|SP>, #<pimm>] Load/Store Load Register Signed Word (Immediate)
0x98000000 ldrsw LDRSW <Xt>, <label> Load Literal Load Register Signed Word (Literal)
0x04200000 ldrt LDRT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Load Register Unprivileged
0xB8203000 ldset LDSET <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Set Word
0xB8204000 ldsmax LDSMAX <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Signed Maximum Word
0xB8205000 ldsmin LDSMIN <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Signed Minimum Word
0xB8400000 ldtr LDTR <Wt>, [<Xn|SP>, #<simm>] Load/Store Load Register (Unprivileged)
0xB8206000 ldumax LDUMAX <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Unsigned Maximum Word
0xB8207000 ldumin LDUMIN <Ws>, <Wt>, [<Xn|SP>] Atomic Atomic Load-Unsigned Minimum Word
0xB8400000 ldur LDUR <Wt>, [<Xn|SP>, #<simm>] Load/Store Load Register (Unscaled)
0x887F7C00 ldxp LDXP <Wt1>, <Wt2>, [<Xn|SP>] Load/Store Excl Load Exclusive Pair
0x885F7C00 ldxr LDXR <Wt>, [<Xn|SP>] Load/Store Excl Load Exclusive Register
0x1AC02000 lsl LSLV <Wd>, <Wn>, <Wm> Data Processing Logical Shift Left (Register)
0x04080000 lsl LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Shift SVE Shift Left (Predicated)
0x01A00010 lsl LSL{S}<c> <Rd>, <Rm>, <Rs> Data Proc Logical Shift Left (A32)
0x1AC02400 lsr LSRV <Wd>, <Wn>, <Wm> Data Processing Logical Shift Right (Register)
0x04090000 lsr LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Shift SVE Logical Shift Right (Predicated)
0x01A00030 lsr LSR{S}<c> <Rd>, <Rm>, <Rs> Data Proc Logical Shift Right (A32)
0x1B000000 madd MADD <Wd>, <Wn>, <Wm>, <Wa> Data Processing Multiply-Add
0x9B000000 madd MADD <Xd>, <Xn>, <Xm>, <Xa> Data Processing Multiply-Add (64-bit)
0x0E000010 mcr MCR<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Coprocessor from Register (A32)
0xFE000010 mcr2 MCR2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Coprocessor from Register 2 (A32)
0x0C400000 mcrr MCRR<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Coprocessor from Two Registers (A32)
0xFC400000 mcrr2 MCRR2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Coprocessor from Two Registers 2 (A32)
0x0E200010 mia MIA<c> <Acc>, <Rn>, <Rm> Coprocessor Multiply with Internal Accumulate
0x0E280010 miaph MIAPH<c> <Acc>, <Rn>, <Rm> Coprocessor Multiply with Internal Accumulate Packed Halfwords
0x0E209400 mla MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Multiply-Accumulate
0xFB000000 mla MLA <Rd>, <Rm>, <Ra>, <Rn> Thumb Mul Multiply Accumulate (Thumb)
0x00200090 mla MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Multiply Accumulate (A32)
0x2E209400 mls MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Multiply-Subtract
0xFB000010 mls MLS <Rd>, <Rm>, <Ra>, <Rn> Thumb Mul Multiply Subtract (Thumb)
0x00600090 mls MLS<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Multiply Subtract (A32)
0x0EA01C00 mov MOV <Vd>.<T>, <Vn>.<T> SIMD Alias Vector Move (Register)
0x6E000400 mov MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] SIMD Copy Move Element to Element
0x03A00000 mov MOV{S}<c> <Rd>, <Operand2> Data Proc Move (A32)
0xEA4F0000 mov.w MOV.W <Rd>, <Operand2> Thumb2 Data Proc Move (Wide)
0x0F000400 movi MOVI <Vd>.<T>, #<imm8> {, lsl #<shift>} SIMD Modified Imm Move Immediate (Vector)
0x72800000 movk MOVK <Wd>, #<imm16> {, lsl #<shift>} Data Processing Move Keep
0x12800000 movn MOVN <Wd>, #<imm16> {, lsl #<shift>} Data Processing Move Not
0x03400000 movt MOVT<c> <Rd>, #<imm16> Data Proc Move Top (A32)
0x03000000 movw MOVW<c> <Rd>, #<imm16> Data Proc Move Word (A32)
0x52800000 movz MOVZ <Wd>, #<imm16> {, lsl #<shift>} Data Processing Move Zero
0x0E100010 mrc MRC<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Register from Coprocessor (A32)
0xFE100010 mrc2 MRC2<c> <coproc>, <opc1>, <Rt>, <CRn>, <CRm>{, <opc2>} Coprocessor Move to Register from Coprocessor 2 (A32)
0x0C500000 mrrc MRRC<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Two Registers from Coprocessor (A32)
0xFC500000 mrrc2 MRRC2<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm> Coprocessor Move to Two Registers from Coprocessor 2 (A32)
0xD5300000 mrrs MRRS <Xt>, <Xt+1>, <sysreg> System Move to Two Registers from System Register (128-bit)
0xD5300000 mrs MRS <Xt>, <system_reg> System Move System Register
0xE1000200 mrs MRS <Rd>, <banked_reg> System Move from Special Register (Banked)
0xF3EF8000 mrs MRS <Rd>, <spec_reg> Thumb System Move Special Register to Register (Thumb)
0x010F0000 mrs MRS<c> <Rd>, <spec_reg> System Move Status Register to Register
0xD5100000 msr MSR <system_reg>, <Xt> System Move to System Register
0xE1200200 msr MSR <banked_reg>, <Rn> System Move to Special Register (Banked)
0x0320F000 msr MSR <spec_reg>, #<imm> System Move Immediate to Special Register (A32)
0xF3800000 msr MSR <spec_reg>, #<imm> Thumb System Move Immediate to Special Register (Thumb)
0xF3808800 msr MSR <spec_reg>, <Rn> Thumb System Move Register to Special Register (Thumb)
0x0120F000 msr MSR<c> <spec_reg>_<fields>, <Rn> System Move Register to Status Register
0xD5100000 msrr MSRR <sysreg>, <Xt>, <Xt+1> System Move Two Registers to System Register (128-bit)
0x1B008000 msub MSUB <Wd>, <Wn>, <Wm>, <Wa> Data Processing Multiply-Subtract
0x0E209C00 mul MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Multiply (Integer)
0x04008000 mul MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Integer Multiply (Predicated)
0x00000090 mul MUL{S}<c> <Rd>, <Rn>, <Rm> Multiply Multiply (A32)
0x2E205800 mvn MVN <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Bitwise NOT
0x03E00000 mvn MVN{S}<c> <Rd>, <Operand2> Data Proc Move NOT (A32)
0xEA6F0000 mvn.w MVN.W <Rd>, <Operand2> Thumb2 Data Proc Move NOT (Wide)
0x2F000400 mvni MVNI <Vd>.<T>, #<imm8> {, lsl #<shift>} SIMD Modified Imm Move NOT Immediate (Vector)
0x042B0000 neg NEG <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Integer Unary SVE Negate
0x2E20B800 neg NEG <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Negate
0xD503201F nop NOP System Alias No Operation
0xBF00 nop NOP Thumb System No Operation (Thumb)
0x0320F000 nop NOP<c> System No Operation (A32)
0x042E0000 not NOT <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Integer Unary SVE Bitwise NOT
0x2E205800 not NOT <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Bitwise NOT
0x2A000000 orn ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise OR NOT
0x0EE01C00 orn ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise OR NOT
0xEA600000 orn.w ORN.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise OR NOT (Wide)
0x32000000 orr ORR <Wd|Wsp>, <Wn>, #<imm> Logical (Immediate) Bitwise OR (Immediate)
0x2A000000 orr ORR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Logical (Register) Bitwise OR (Shifted Register)
0x0EA01C00 orr ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Bitwise OR
0x040D0000 orr ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Logic SVE Bitwise OR (Predicated)
0x03800000 orr ORR{S}<c> <Rd>, <Rn>, <Operand2> Data Proc Logical OR (A32)
0xEA400000 orr.w ORR.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Bitwise OR (Wide)
0x04060000 orv ORV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Bitwise OR Reduction
0xDAC303E0 pacda PACDA <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Data A)
0xDAC10800 pacda PACDA <Xd>, <Xn> Data Processing Pointer Authentication Code for Data Address (Key A)
0xDAC303E0 pacdb PACDB <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Data B)
0xDAC10C00 pacdb PACDB <Xd>, <Xn> Data Processing Pointer Authentication Code for Data Address (Key B)
0x9AC03000 pacga PACGA <Xd>, <Xn>, <Xm> Data Processing Pointer Authentication Code Generic Address
0xDAC103E0 pacia PACIA <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Inst A)
0xDAC10000 pacia PACIA <Xd>, <Xn> Data Processing Pointer Authentication Code for Instruction Address (Key A)
0xDAC103E0 pacib PACIB <Xd>, <Xn|SP> Data Processing Pointer Authentication Code (Inst B)
0xDAC10400 pacib PACIB <Xd>, <Xn> Data Processing Pointer Authentication Code for Instruction Address (Key B)
0x2518E000 pfalse PFALSE <Pd>.B SVE Predicate SVE Initialize Predicate to False
0x25190000 pfirst PFIRST <Pd>.B, <Pg>, <Pn>.B SVE Predicate SVE Predicate First Active
0x06800010 pkhbt PKHBT<c> <Rd>, <Rn>, <Rm> {, LSL #<imm>} Data Proc Pack Halfword Bottom Top
0x06800050 pkhtb PKHTB<c> <Rd>, <Rn>, <Rm> {, ASR #<imm>} Data Proc Pack Halfword Top Bottom
0xF550F000 pld PLD [<Rn>, #<imm>] Load/Store Preload Data
0xF510F000 pldw PLDW [<Rn>, #<imm>] Load/Store Preload Data for Write (A32)
0xF890F000 pldw PLDW [<Rn>, #<imm>] Thumb Load/Store Preload Data for Write (Thumb)
0xF450F000 pli PLI [<Rn>, #<imm>] Load/Store Preload Instruction
0x2E209C00 pmul PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Polynomial Multiply
0x0E20E000 pmull PMULL <Vd>.1Q, <Vn>.1D, <Vm>.1D Crypto Polynomial Multiply Long (A64)
0x0E20E000 pmull PMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Polynomial Multiply Long
0x251B0000 pnext PNEXT <Pdn>.<T>, <Pg>, <Pdn>.<T> SVE Predicate SVE Find Next Active Predicate
0xBC00 pop POP <registers> Thumb Load Multiple Pop (Thumb)
0x08BD0000 pop POP<c> <registers> Load Multiple Pop Multiple Registers (A32)
0xE8BD0000 pop.w POP.W <registers> Thumb Load Multiple Pop (Wide)
0xF9800000 prfm PRFM <prfop>, [<Xn|SP>, #<pimm>] Load/Store Imm Prefetch Memory (Immediate)
0xD8000000 prfm PRFM <prfop>, <label> Load Literal Prefetch Memory (Literal)
0xF8A00000 prfm PRFM <prfop>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Prefetch Memory (Register)
0xD503223F psb PSB CSYNC System Alias Profiling Synchronization Barrier
0xF57FF044 pssbb PSSBB System Hint Physical Speculative Store Bypass Barrier (A32)
0xD503209F pssbb PSSBB System Hint Physical Speculation Barrier
0x25180000 ptest PTEST <Pg>, <Pn>.B SVE Predicate SVE Predicate Test
0x25180000 ptrue PTRUE <Pd>.<T> {, <pattern>} SVE Predicate SVE Initialize Predicate to True
0xB400 push PUSH <registers> Thumb Store Multiple Push (Thumb)
0x092D0000 push PUSH<c> <registers> Store Multiple Push Multiple Registers (A32)
0xE92D0000 push.w PUSH.W <registers> Thumb Store Multiple Push (Wide)
0x01000050 qadd QADD<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Add (A32)
0x06200F10 qadd16 QADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Add 16
0x06200F90 qadd8 QADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Add 8
0x01400050 qdadd QDADD<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Double and Add
0x01600050 qdsub QDSUB<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Double and Subtract
0x01200050 qsub QSUB<c> <Rd>, <Rm>, <Rn> Data Proc Saturating Subtract (A32)
0x06200F70 qsub16 QSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Subtract 16
0x06200FF0 qsub8 QSUB8<c> <Rd>, <Rn>, <Rm> SIMD Integer Saturating Subtract 8
0x050B0000 rbit RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> SVE Permute SVE Reverse Bits
0x5AC00000 rbit RBIT <Wd>, <Wn> Data Processing Reverse Bits
0xFA90F0A0 rbit RBIT <Rd>, <Rm> Thumb Misc Reverse Bits (Thumb)
0xDAC00000 rbit RBIT <Xd>, <Xn> Data Processing Reverse Bits (64-bit)
0x06FF0F30 rbit RBIT<c> <Rd>, <Rm> Data Proc Reverse Bits (A32)
0x383F0000 rcw RCW <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write (128-bit)
0x38200000 rcw RCW <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write
0x38A00000 rcwa RCWA <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write (Acquire)
0x38A04000 rcwal RCWAL <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write (Acquire-Release)
0x38204000 rcws RCWS <Xt>, <Xt+1>, [<Xn>] Atomic Read Check Write (Soft)
0xD65F0000 ret RET {<Xn>} Branch Return from Subroutine
0x05260000 rev REV <Zd>.<T>, <Zn>.<T> SVE Permute SVE Reverse Vector
0xBA00 rev REV <Rd>, <Rm> Thumb Data Proc Reverse Bytes (Thumb)
0x5AC00400 rev REV <Wd>, <Wn> Data Processing Reverse Bytes
0xDAC00C00 rev REV <Xd>, <Xn> Data Processing Reverse Bytes (64-bit)
0xFA90F080 rev REV <Rd>, <Rm> Thumb Misc Reverse Bytes (Thumb)
0x5AC00800 rev REV <Wd>, <Wn> Data Processing Reverse Bytes (32-bit)
0x06BF0F30 rev REV<c> <Rd>, <Rm> Data Proc Reverse Bytes (A32)
0xBA40 rev16 REV16 <Rd>, <Rm> Thumb Data Proc Reverse Bytes Halfword (Thumb)
0x5AC00400 rev16 REV16 <Wd>, <Wn> Data Processing Reverse Bytes in Halfwords
0xFA90F090 rev16 REV16 <Rd>, <Rm> Thumb Misc Reverse Bytes in Halfwords (Thumb)
0xDAC00800 rev32 REV32 <Xd>, <Xn> Data Processing Reverse Bytes in Words
0x05080000 revb REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> SVE Permute SVE Reverse Bytes in Elements
0x05090000 revh REVH <Zd>.<T>, <Pg>/M, <Zn>.<T> SVE Permute SVE Reverse Halfwords in Elements
0xBAC0 revsh REVSH <Rd>, <Rm> Thumb Data Proc Reverse Signed Halfword (Thumb)
0xFA90F0B0 revsh REVSH <Rd>, <Rm> Thumb Misc Reverse Signed Halfword (Thumb)
0x050A0000 revw REVW <Zd>.D, <Pg>/M, <Zn>.D SVE Permute SVE Reverse Words in Elements
0xF8100A00 rfe RFE<c> <Rn>{!} System Return From Exception
0xBA000000 rmif RMIF <Xn>, #<shift>, #<mask> Data Processing Rotate Mask Insert Flags
0xD53B2400 rndr RNDR <Xt> System Random Number
0xD53B2600 rndrrs RNDRRS <Xt> System Random Number Reseed
0x01A00070 ror ROR{S}<c> <Rd>, <Rm>, <Rs> Data Proc Rotate Right (A32)
0x1AC02C00 rorv RORV <Wd>, <Wn>, <Wm> Data Processing Rotate Right (Register)
0x01A00060 rrx RRX{S}<c> <Rd>, <Rm> Data Proc Rotate Right with Extend (A32)
0xEA5F0000 rrx RRX{S}.W <Rd>, <Rm> Thumb2 Data Proc Rotate Right with Extend (Thumb)
0x4240 rsb RSB <Rd>, <Rn>, #0 Thumb Data Proc Reverse Subtract (Thumb)
0x02600000 rsb RSB{S}<c> <Rd>, <Rn>, <Operand2> Data Proc Reverse Subtract (A32)
0xEBC00000 rsb.w RSB.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Reverse Subtract (Wide)
0x02E00000 rsc RSC{S}<c> <Rd>, <Rn>, <Operand2> Data Proc Reverse Subtract with Carry (A32)
0x06100F10 sadd16 SADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Add 16 (A32)
0x06100F90 sadd8 SADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Add 8 (A32)
0x0E200000 saddl SADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Add Long
0x04000000 saddv SADDV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Signed Integer Add Reduction
0x0E201000 saddw SADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> SIMD Three Register Diff Signed Add Wide
0xF57FF070 sb SB System Hint Speculation Barrier (A32)
0xD50330FF sb SB System Hint Speculation Barrier
0x5A000000 sbc SBC <Wd>, <Wn>, <Wm> Data Processing Subtract with Carry
0x02C00000 sbc SBC{S}<c> <Rd>, <Rn>, <Operand2> Data Proc Subtract with Carry (A32)
0xEB600000 sbc.w SBC.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Subtract with Carry (Wide)
0x7A000000 sbcs SBCS <Wd>, <Wn>, <Wm> Data Processing Subtract with Carry and Set Flags
0x13000000 sbfm SBFM <Wd>, <Wn>, #<immr>, #<imms> Bitfield Signed Bitfield Move
0x07A00050 sbfx SBFX<c> <Rd>, <Rn>, #<lsb>, #<width> Data Proc Signed Bit Field Extract (A32)
0xF3400000 sbfx SBFX <Rd>, <Rn>, #<lsb>, #<width> Thumb Bitfield Signed Bit Field Extract (Thumb)
0x65560000 scvtf SCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Conversion SVE Signed Integer Convert to Floating-Point
0x1E220000 scvtf SCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} FP Conversion Signed Integer Convert to Floating-Point
0x9E220000 scvtf SCVTF <Dd>, <Xn> Float Conversion Signed Integer Convert to Floating-point
0x04800000 sdiv SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Signed Divide
0x1AC00C00 sdiv SDIV <Wd>, <Wn>, <Wm> Data Processing Signed Divide
0xFB90F0F0 sdiv SDIV <Rd>, <Rn>, <Rm> Thumb Div Signed Divide (Thumb)
0x0710F010 sdiv SDIV<c> <Rd>, <Rn>, <Rm> Data Proc Signed Divide (A32)
0x44000000 sdot SDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> SVE Dot Product SVE Signed Dot Product
0xFC200D00 sdot SDOT<c>.S8 <Qd>, <Qn>, <Qm> NEON 3-Reg Signed Dot Product (A32)
0x4E809400 sdot SDOT <Vd>.4S, <Vn>.16B, <Vm>.16B NEON DotProd Signed Dot Product (NEON)
0xC18E0000 sdot SDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B SME2 DotProd Signed Dot Product (Multi-vector)
0x05000000 sel SEL <Zd>.<T>, <Pg>, <Zn>.<T>, <Zm>.<T> SVE Select SVE Select Elements
0x068000B0 sel SEL<c> <Rd>, <Rn>, <Rm> Data Proc Select Bytes
0xF1010000 setend SETEND <endian> System Set Endianness
0xB650 setend SETEND <endian> Thumb System Set Endianness (Thumb)
0x3A00480D setf16 SETF16 <Wn> System Set Flags 16-bit
0x3A00080D setf8 SETF8 <Wn> System Set Flags 8-bit
0xF1100000 setpan SETPAN #<imm> System Set Privileged Access Never (A32)
0xD503209F sev SEV System Alias Send Event
0x0320F004 sev SEV System Hint Send Event (A32)
0xBF40 sev SEV Thumb System Send Event (Thumb)
0xD50320BF sevl SEVL System Alias Send Event Local
0x0320F005 sevl SEVL System Hint Send Event Local (A32)
0xBF50 sevl SEVL Thumb System Send Event Local (Thumb)
0xF2000300 sha1c SHA1C.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA1 Choose (A32)
0x5E000000 sha1c SHA1C <Qd>, <Sn>, <Vm>.4S Crypto SHA1 Choose (A64)
0x5E000000 sha1c SHA1C <Qd>, <Sn>, <Vm>.<T> Crypto SHA1 Choose
0xF3BA0280 sha1h SHA1H.32 <Qd>, <Qm> Crypto 2-Reg SHA1 Hash Update (A32)
0x5E280800 sha1h SHA1H <Sd>, <Sn> Crypto SHA1 Hash Update (A64)
0xF2200300 sha1m SHA1M.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA1 Majority (A32)
0x5E002000 sha1m SHA1M <Qd>, <Sn>, <Vm>.<T> Crypto SHA1 Majority
0xF2100300 sha1p SHA1P.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA1 Parity (A32)
0x5E001000 sha1p SHA1P <Qd>, <Sn>, <Vm>.<T> Crypto SHA1 Parity
0xF3000C00 sha256h SHA256H.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA256 Hash Part 1 (A32)
0x5E004000 sha256h SHA256H <Qd>, <Qn>, <Vm>.4S Crypto SHA256 Hash Part 1 (A64)
0x5E004000 sha256h SHA256H <Qd>, <Qn>, <Vm>.<T> Crypto SHA256 Hash Part 1
0xF3000C10 sha256h2 SHA256H2.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA256 Hash Part 2 (A32)
0x5E005000 sha256h2 SHA256H2 <Qd>, <Qn>, <Vm>.4S Crypto SHA256 Hash Part 2 (A64)
0x5E005000 sha256h2 SHA256H2 <Qd>, <Qn>, <Vm>.<T> Crypto SHA256 Hash Part 2
0xF3BA0400 sha256su0 SHA256SU0.32 <Qd>, <Qm> Crypto 2-Reg SHA256 Schedule Update 0 (A32)
0xF3000C00 sha256su1 SHA256SU1.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA256 Schedule Update 1 (A32)
0xF3200C00 sha512h SHA512H.64 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA512 Hash Part 1 (A32)
0xF3200C10 sha512h2 SHA512H2.64 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA512 Hash Part 2 (A32)
0xF3BA0600 sha512su0 SHA512SU0.64 <Qd>, <Qm> Crypto 2-Reg SHA512 Schedule Update 0 (A32)
0xF3200D00 sha512su1 SHA512SU1.64 <Qd>, <Qn>, <Qm> Crypto 3-Reg SHA512 Schedule Update 1 (A32)
0x06300F10 shadd16 SHADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Halving Add 16
0x06300F90 shadd8 SHADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Halving Add 8
0x0F005400 shl SHL <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Vector Shift Left (Immediate)
0x2F00A400 shll SHLL <Vd>.<Td>, <Vn>.<Ts>, #<shift> SIMD Shift Imm Shift Left Long
0x0F008400 shrn SHRN <Vd>.<Tb>, <Vn>.<Ta>, #<shift> SIMD Shift Imm Shift Right Narrow
0x06300F70 shsub16 SHSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Halving Subtract 16
0x06300FF0 shsub8 SHSUB8<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Halving Subtract 8
0x2F005400 sli SLI <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shift Left and Insert
0xF2200C10 sm3partw1 SM3PARTW1.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SM3 Part Word 1 (A32)
0xF2200D10 sm3partw2 SM3PARTW2.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SM3 Part Word 2 (A32)
0xF2200C00 sm3ss1 SM3SS1.32 <Qd>, <Qn>, <Qm> Crypto 3-Reg SM3 Step 1 (A32)
0xFE800800 sm3tt1a SM3TT1A.32 <Qd>, <Dn>, <Dm>, #<imm> Crypto Imm SM3 Step 2A (A32)
0xFE800810 sm3tt1b SM3TT1B.32 <Qd>, <Dn>, <Dm>, #<imm> Crypto Imm SM3 Step 2B (A32)
0xFE900800 sm3tt2a SM3TT2A.32 <Qd>, <Dn>, <Dm>, #<imm> Crypto Imm SM3 Step 3A (A32)
0xFE900810 sm3tt2b SM3TT2B.32 <Qd>, <Dn>, <Dm>, #<imm> Crypto Imm SM3 Step 3B (A32)
0xF3BA0480 sm4e SM4E.32 <Qd>, <Qm> Crypto 2-Reg SM4 Encrypt (A32)
0xF3BA0580 sm4ekey SM4EKEY.32 <Qd>, <Qm> Crypto 2-Reg SM4 Key (A32)
0x9B200000 smaddl SMADDL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Signed Multiply-Add Long
0x04040000 smax SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Signed Maximum
0x0E206400 smax SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Maximum
0x04010000 smaxv SMAXV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Signed Maximum Reduction
0x0E31A800 smaxv SMAXV <V><d>, <Vn>.<T> SIMD Across Lane Vector Signed Maximum Across
0x01600070 smc SMC<c> #<imm> System Secure Monitor Call (A32)
0xF7F08000 smc SMC #<imm> Thumb System Secure Monitor Call (Thumb)
0x04050000 smin SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Signed Minimum
0x0E206800 smin SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Minimum
0x04030000 sminv SMINV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Signed Minimum Reduction
0x01000080 smlabb SMLABB<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Bottom x Bottom)
0x010000C0 smlabt SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Bottom x Top)
0x07000010 smlad SMLAD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate Dual
0xFBC00000 smlal SMLAL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Signed Multiply Accumulate Long (Thumb)
0x0E208000 smlal SMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Multiply-Accumulate Long
0x01400080 smlalbb SMLALBB<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Bottom x Bottom)
0x014000C0 smlalbt SMLALBT<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Bottom x Top)
0x07400010 smlald SMLALD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long Dual
0x014000A0 smlaltb SMLALTB<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Top x Bottom)
0x014000E0 smlaltt SMLALTT<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Accumulate Long (Top x Top)
0x010000A0 smlatb SMLATB<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Top x Bottom)
0x010000E0 smlatt SMLATT<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Top x Top)
0x01200080 smlawb SMLAWB<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Word x Bottom)
0x012000C0 smlawt SMLAWT<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Accumulate (Word x Top)
0x07000050 smlsd SMLSD{X}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Multiply Subtract Dual
0x07400050 smlsld SMLSLD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Signed Multiply Subtract Long Dual
0x4E40A400 smmla SMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Signed Integer Matrix Multiply-Accumulate (NEON)
0x07500010 smmla SMMLA{R}<c> <Rd>, <Rn>, <Rm>, <Ra> Multiply Signed Most Significant Word Multiply Accumulate
0x0750F010 smmul SMMUL{R}<c> <Rd>, <Rn>, <Rm> Multiply Signed Most Significant Word Multiply
0x9B208000 smsubl SMSUBL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Signed Multiply-Subtract Long
0x0700F010 smuad SMUAD{X}<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply Add Dual
0x01600080 smulbb SMULBB<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Bottom x Bottom)
0x016000C0 smulbt SMULBT<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Bottom x Top)
0x9B407C00 smulh SMULH <Xd>, <Xn>, <Xm> Data Processing Signed Multiply High
0xFB800000 smull SMULL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Signed Multiply Long (Thumb)
0x0E20C000 smull SMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Multiply Long
0x016000A0 smultb SMULTB<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Top x Bottom)
0x016000E0 smultt SMULTT<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Top x Top)
0x012000A0 smulwb SMULWB<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Word x Bottom)
0x012000E0 smulwt SMULWT<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply (Word x Top)
0x0700F050 smusd SMUSD{X}<c> <Rd>, <Rn>, <Rm> Multiply Signed Multiply Subtract Dual
0x05AD0000 splice SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T> SVE Permute SVE Splice Vectors
0x0E200C00 sqadd SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Saturating Add
0x0E202C00 sqsub SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Signed Saturating Subtract
0x0F009200 sqxtn SQXTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Signed Saturating Extract Narrow
0x2F004400 sri SRI <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Shift Right and Insert
0xF8CD0500 srs SRS<c> SP{!}, #<mode> System Store Return State
0x06A00010 ssat SSAT<c> <Rd>, #<imm>, <Rm> {, <shift>} Data Proc Signed Saturate (A32)
0x06A00F30 ssat16 SSAT16<c> <Rd>, #<imm>, <Rm> Data Proc Signed Saturate 16 (A32)
0xF57FF040 ssbb SSBB System Hint Speculative Store Bypass Barrier (A32)
0x0F000400 sshr SSHR <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Vector Signed Shift Right
0x0F001400 ssra SSRA <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Signed Shift Right and Accumulate
0x06100F70 ssub16 SSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Signed Subtract 16 (A32)
0x0E202000 ssubl SSUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Signed Subtract Long
0x0D000000 st1 ST1 { <Vt>.<T>, ... }, [<Xn|SP>] SIMD Load/Store Store Multiple Single Elements
0xE4000000 st1b ST1B { <Zt>.B }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Bytes
0xE4C00000 st1d ST1D { <Zt>.D }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Doublewords
0xE4400000 st1h ST1H { <Zt>.H }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Halfwords
0xE4800000 st1w ST1W { <Zt>.S }, <Pg>, [<Xn|SP>] SVE Store SVE Store Contiguous Words
0xE4800000 st1w ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, SXTW #<shift>] SVE Scatter SVE Scatter Store Words (Vector Index)
0x0C000000 st2 ST2 { <Vt1>.<T>, <Vt2>.<T> }, [<Xn|SP>] SIMD Load/Store Store Multiple 2-Element Structures
0xD9200C00 st2g ST2G <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag Two
0xD9600000 st2g ST2G <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag (Two Granules)
0x0C002000 st3 ST3 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>] SIMD Load/Store Store Multiple 3-Element Structures
0x0C004000 st4 ST4 { <Vt1>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>] SIMD Load/Store Store Multiple 4-Element Structures
0xF81F7800 st64b ST64B <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Store
0xF81F7800 st64bv ST64BV <Ws>, <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Store with Return
0xF81F7C00 st64bv0 ST64BV0 <Ws>, <Xt>, [<Xn|SP>] Load/Store Single-copy Atomic 64-byte Store with Return (Zero)
0x0C000000 stc STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Store Coprocessor (A32)
0xFD000000 stc2 STC2{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!} Coprocessor Store Coprocessor 2 (A32)
0xD9200400 stg STG <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag
0xD9200000 stg STG <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag
0x69002000 stgp STGP <Xt>, <Xt2>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag and Pair
0x01800F9F stl STL<c> <Rt>, [<Rn>] Load/Store Store Release (A32)
0x01800F90 stlex STLEX<c> <Rd>, <Rt>, [<Rn>] Load/Store Store Release Exclusive (A32)
0x01C00F90 stlexb STLEXB<c> <Rd>, <Rt>, [<Rn>] Store Excl Store Release Exclusive Byte (A32)
0x01A00F90 stlexd STLEXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] Store Excl Store Release Exclusive Double (A32)
0x01E00F90 stlexh STLEXH<c> <Rd>, <Rt>, [<Rn>] Store Excl Store Release Exclusive Halfword (A32)
0x089F F?? stlr STLR <Wt>, [<Xn|SP>] Load/Store Store-Release Register
0x08BF F?? stlrb STLRB <Wt>, [<Xn|SP>] Load/Store Store-Release Register Byte
0x48BF F?? stlrh STLRH <Wt>, [<Xn|SP>] Load/Store Store-Release Register Halfword
0x08007C00 stlxr STLXR <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store-Release Exclusive Register
0x08007C00 stlxrb STLXRB <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store-Release Exclusive Register Byte
0x48007C00 stlxrh STLXRH <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store-Release Exclusive Register Halfword
0xC000 stm STM <Rn>!, <registers> Thumb Store Multiple Store Multiple (Thumb)
0x08000000 stm STM<mode><c> <Rn>{!}, <registers> Store Multiple Store Multiple (A32)
0xE8800000 stm.w STM.W <Rn>{!}, <registers> Thumb Store Multiple Store Multiple (Wide)
0x28000000 stnp STNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair (Non-temporal)
0x2D000000 stp STP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair SIMD&FP Registers
0x29000000 stp STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair of Registers
0xA9000000 stp STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>] Load/Store Pair Store Pair of Registers (64-bit)
0xBD000000 str STR <Bt|Ht|St|Dt|Qt>, [<Xn|SP>, #<pimm>] Load/Store Store SIMD&FP Register (Immediate)
0xB9000000 str STR <Wt>, [<Xn|SP>, #<pimm>] Load/Store Imm Store Register (Immediate)
0xB8200800 str STR <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Reg Store Register (Register)
0x04000000 str STR<c> <Rt>, [<Rn>, #+/-<imm>]{!} Load/Store Store Register (A32)
0xF8C00000 str.w STR.W <Rt>, [<Rn>, #<imm>] Thumb Store Store Register (Wide)
0x39000000 strb STRB <Wt>, [<Xn|SP>, #<pimm>] Load/Store Store Register Byte (Immediate)
0x38200800 strb STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Store Register Byte (Register)
0xF8800000 strb.w STRB.W <Rt>, [<Rn>, #<imm>] Thumb Store Store Register Byte (Wide)
0x04600000 strbt STRBT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Store Register Byte Unprivileged
0xE9C00000 strd STRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>] Thumb Store Store Register Dual (Thumb)
0xE8400000 strex STREX <Rd>, <Rt>, [<Rn>] Thumb Store Excl Store Register Exclusive (Thumb)
0x01C00F90 strexb STREXB<c> <Rd>, <Rt>, [<Rn>] Load/Store Excl Store Register Exclusive Byte (A32)
0xE8C00F40 strexb STREXB <Rd>, <Rt>, [<Rn>] Thumb Store Excl Store Register Exclusive Byte (Thumb)
0x01A00F90 strexd STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>] Load/Store Excl Store Register Exclusive Double (A32)
0x01E00F90 strexh STREXH<c> <Rd>, <Rt>, [<Rn>] Load/Store Excl Store Register Exclusive Halfword (A32)
0xE8C00F50 strexh STREXH <Rd>, <Rt>, [<Rn>] Thumb Store Excl Store Register Exclusive Halfword (Thumb)
0x79000000 strh STRH <Wt>, [<Xn|SP>, #<pimm>] Load/Store Store Register Halfword (Immediate)
0x78200800 strh STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}] Load/Store Store Register Halfword (Register)
0xF8A00000 strh.w STRH.W <Rt>, [<Rn>, #<imm>] Thumb Store Store Register Halfword (Wide)
0x002000B0 strht STRHT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Store Register Halfword Unprivileged
0x04200000 strt STRT<c> <Rt>, [<Rn>, #+/-<imm>] Load/Store Store Register Unprivileged
0xB8000000 sttr STTR <Wt>, [<Xn|SP>, #<simm>] Load/Store Store Register (Unprivileged)
0x38000000 sttrb STTRB <Wt>, [<Xn|SP>, #<simm>] Load/Store Store Register Byte (Unprivileged)
0x78000000 sttrh STTRH <Wt>, [<Xn|SP>, #<simm>] Load/Store Store Register Halfword (Unprivileged)
0xB8000000 stur STUR <Wt>, [<Xn|SP>, #<simm>] Load/Store Store Register (Unscaled)
0x38000000 sturb STURB <Wt>, [<Xn|SP>, #<simm>] Load/Store Store Register Byte (Unscaled)
0x78000000 sturh STURH <Wt>, [<Xn|SP>, #<simm>] Load/Store Store Register Halfword (Unscaled)
0x88207C00 stxp STXP <Ws>, <Wt1>, <Wt2>, [<Xn|SP>] Load/Store Excl Store Exclusive Pair
0x88007C00 stxr STXR <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store Exclusive Register
0x08007C00 stxrb STXRB <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store Exclusive Register Byte
0x48007C00 stxrh STXRH <Ws>, <Wt>, [<Xn|SP>] Load/Store Excl Store Exclusive Register Halfword
0xD9200C00 stz2g STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag and Zero Two
0xD9400000 stz2g STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag and Zero (Two Granules)
0xD9200800 stzg STZG <Xt|SP>, [<Xn|SP>, #<simm>] Load/Store Store Allocation Tag and Zero
0x4B200000 sub SUB <Wd|Wsp>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} Data Processing Subtract (Extended Register)
0x51000000 sub SUB <Wd|Wsp>, <Wn|Wsp>, #<imm> {, lsl #<shift>} Data Processing Subtract (Immediate)
0x4B000000 sub SUB <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Data Processing Subtract (Shifted Register)
0x2E208400 sub SUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Subtract (Integer)
0x04004000 sub SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Integer Subtract (Predicated)
0x02400000 sub SUB{S}<c> <Rd>, <Rn>, <Operand2> Data Proc Subtract (A32)
0xEBA00000 sub.w SUB.W <Rd>, <Rn>, <Operand2> Thumb2 Data Proc Subtract (Wide)
0xD1000000 subg SUBG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> Data Processing Subtract with Tag
0x9A000000 subp SUBP <Xd>, <Xn|SP>, <Xm|SP> Data Processing Subtract Pointers
0x9AC00000 subp SUBP <Xd>, <Xn|SP>, <Xm|SP> Data Processing Subtract Pointer
0x6B200000 subs SUBS <Wd>, <Wn|Wsp>, <Wm> {, <extend> {#<amount>}} Data Processing Subtract and Set Flags (Extended)
0x71000000 subs SUBS <Wd>, <Wn|Wsp>, #<imm> {, lsl #<shift>} Data Processing Subtract and Set Flags (Immediate)
0x6B000000 subs SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>} Data Processing Subtract and Set Flags (Shifted)
0x025EF000 subs SUBS PC, LR, #<imm> Data Proc Subtract and Return (A32)
0xF3DE8F00 subs SUBS PC, LR, #<imm> Thumb Data Proc Subtract and Return (Thumb)
0x4F409C00 sudot SUDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>[<index>] NEON 3-Reg Signed-Unsigned Dot Product (NEON)
0x05242000 sunpkhi SUNPKHI <Zd>.<T>, <Zn>.<Tb> SVE Permute SVE Signed Unpack High
0x05240000 sunpklo SUNPKLO <Zd>.<T>, <Zn>.<Tb> SVE Permute SVE Signed Unpack Low
0xD4000001 svc SVC #<imm> Exception Supervisor Call
0xDF00 svc SVC #<imm> Thumb System Supervisor Call (Thumb)
0x0F000000 svc SVC<c> #<imm> System Supervisor Call (A32)
0xB8208000 swp SWP <Ws>, <Wt>, [<Xn|SP>] Atomic Swap Word
0x01000090 swp SWP<c> <Rt>, <Rt2>, [<Rn>] Load/Store Swap (A32)
0x06A00070 sxtab SXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Signed Extend and Add Byte
0x06800070 sxtab16 SXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Signed Extend and Add Byte 16
0x06B00070 sxtah SXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Signed Extend and Add Halfword
0xB240 sxtb SXTB <Rd>, <Rm> Thumb Data Proc Signed Extend Byte (Thumb)
0x06AF0070 sxtb SXTB<c> <Rd>, <Rm> {, <rotation>} Data Proc Signed Extend Byte (A32)
0x13001C00 sxtb SXTB <Wd>, <Wn> Bitfield Sign Extend Byte
0x068F0070 sxtb16 SXTB16<c> <Rd>, <Rm> {, <rotation>} Data Proc Signed Extend Byte 16 (A32)
0xB200 sxth SXTH <Rd>, <Rm> Thumb Data Proc Signed Extend Halfword (Thumb)
0x06BF0070 sxth SXTH<c> <Rd>, <Rm> {, <rotation>} Data Proc Signed Extend Halfword (A32)
0x93407C00 sxtw SXTW <Xd>, <Wn> Bitfield Sign Extend Word
0xD5080000 sys SYS #<op1>, Cn, Cm, #<op2> {, <Xt>} System System Instruction
0xE8D0F000 tbb TBB [<Rn>, <Rm>] Thumb Branch Table Branch Byte
0xE8D0F010 tbh TBH [<Rn>, <Rm>, LSL #1] Thumb Branch Table Branch Halfword
0x0E000000 tbl TBL <Vd>.<T>, { <Vn>.16B, ... }, <Vm>.<T> SIMD Table Vector Table Lookup
0x05200000 tbl TBL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Table Lookup
0x37000000 tbnz TBNZ <Wt|Xt>, #<imm>, <label> Branch Test Bit Not Zero
0x36000000 tbz TBZ <Wt|Xt>, #<imm>, <label> Branch Test Bit Zero
0xD503337F tcommit TCOMMIT System Transaction Commit
0x03300000 teq TEQ<c> <Rn>, <Operand2> Data Proc Test Equivalence (A32)
0xEA900F00 teq.w TEQ.W <Rn>, <Operand2> Thumb2 Data Proc Test Equivalence (Wide)
0xD508831F tlbi TLBI VMALLE1IS System TLB Invalidate (All)
0xD5088720 tlbi TLBI VAE1, <Xt> System TLB Invalidate (VA)
0xD5080000 tlbi TLBI <op> {, <Xt>} System Alias TLB Invalidate
0xD5031E00 trcit TRCIT <Xt> System Trace Instrumentation
0x0E002800 trn1 TRN1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Transpose 1
0x05300000 trn1 TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Transpose 1
0x0E006800 trn2 TRN2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Transpose 2
0x05310000 trn2 TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Transpose 2
0xF57FF048 tsb TSB CSYNC System Hint Trace Synchronization Barrier (A32)
0xD503225F tsb TSB CSYNC System Hint Trace Synchronization Barrier
0x03100000 tst TST<c> <Rn>, <Operand2> Data Proc Test (A32)
0xEA100F00 tst.w TST.W <Rn>, <Operand2> Thumb2 Data Proc Test (Wide)
0xD52B33?? tstart TSTART <Xd> System Transaction Start
0xD52B33?? ttest TTEST <Xd> System Transaction Test
0x06500F10 uadd16 UADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Add 16 (A32)
0x06500F90 uadd8 UADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Add 8 (A32)
0x2E200000 uaddl UADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Add Long
0x04200000 uaddv UADDV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Unsigned Integer Add Reduction
0x2E201000 uaddw UADDW <Vd>.<Td>, <Vn>.<Td>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Add Wide
0x53000000 ubfm UBFM <Wd>, <Wn>, #<immr>, #<imms> Bitfield Unsigned Bitfield Move
0x07E00050 ubfx UBFX<c> <Rd>, <Rn>, #<lsb>, #<width> Data Proc Unsigned Bit Field Extract (A32)
0xF3C00000 ubfx UBFX <Rd>, <Rn>, #<lsb>, #<width> Thumb Bitfield Unsigned Bit Field Extract (Thumb)
0x65570000 ucvtf UCVTF <Zdn>.<T>, <Pg>/M, <Zdn>.<T> SVE Conversion SVE Unsigned Integer Convert to Floating-Point
0x1E230000 ucvtf UCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>} FP Conversion Unsigned Integer Convert to Floating-Point
0xE7F000F0 udf UDF #<imm> System Undefined Instruction
0xDE00 udf UDF #<imm> Thumb System Undefined Instruction (Thumb)
0x04810000 udiv UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Unsigned Divide
0x1AC00800 udiv UDIV <Wd>, <Wn>, <Wm> Data Processing Unsigned Divide
0xFBB0F0F0 udiv UDIV <Rd>, <Rn>, <Rm> Thumb Div Unsigned Divide (Thumb)
0x0730F010 udiv UDIV<c> <Rd>, <Rn>, <Rm> Data Proc Unsigned Divide (A32)
0x44004000 udot UDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb> SVE Dot Product SVE Unsigned Dot Product
0xFC200D10 udot UDOT<c>.U8 <Qd>, <Qn>, <Qm> NEON 3-Reg Unsigned Dot Product (A32)
0x6E809400 udot UDOT <Vd>.4S, <Vn>.16B, <Vm>.16B NEON DotProd Unsigned Dot Product (NEON)
0xC18E8000 udot UDOT { <Zd1>.S-<Zd2>.S }, <Zn>.B, <Zm>.B SME2 DotProd Unsigned Dot Product (Multi-vector)
0x06700F10 uhadd16 UHADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Halving Add 16
0x06700F90 uhadd8 UHADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Halving Add 8
0x06700F70 uhsub16 UHSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Halving Subtract 16
0x06700FF0 uhsub8 UHSUB8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Halving Subtract 8
0x00400090 umaal UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Unsigned Multiply Accumulate Accumulate Long
0x9BA00000 umaddl UMADDL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Unsigned Multiply-Add Long
0x04060000 umax UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Unsigned Maximum
0x2E206400 umax UMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Maximum
0x04020000 umaxv UMAXV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Unsigned Maximum Reduction
0x04070000 umin UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> SVE Integer Binary SVE Unsigned Minimum
0x2E206800 umin UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Minimum
0x04040000 uminv UMINV <Vd>, <Pg>, <Zn>.<T> SVE Reduction SVE Unsigned Minimum Reduction
0x2E31A800 uminv UMINV <V><d>, <Vn>.<T> SIMD Across Lane Vector Unsigned Minimum Across
0xFBE00000 umlal UMLAL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Unsigned Multiply Accumulate Long (Thumb)
0x00A00090 umlal UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Unsigned Multiply Accumulate Long (A32)
0x2E208000 umlal UMLAL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Multiply-Accumulate Long
0x4E40AC00 ummla UMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Unsigned Integer Matrix Multiply-Accumulate (NEON)
0x9BA08000 umsubl UMSUBL <Xd>, <Wn>, <Wm>, <Xa> Data Processing Unsigned Multiply-Subtract Long
0x9BC07C00 umulh UMULH <Xd>, <Xn>, <Xm> Data Processing Unsigned Multiply High
0xFBA00000 umull UMULL <RdLo>, <RdHi>, <Rn>, <Rm> Thumb Mul Unsigned Multiply Long (Thumb)
0x00800090 umull UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm> Multiply Unsigned Multiply Long (A32)
0x2E20C000 umull UMULL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Multiply Long
0x2E200C00 uqadd UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Saturating Add
0x06600F10 uqadd16 UQADD16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Add 16
0x06600F90 uqadd8 UQADD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Add 8
0x2E202C00 uqsub UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Three Register Vector Unsigned Saturating Subtract
0x06600F70 uqsub16 UQSUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Subtract 16
0x06600FF0 uqsub8 UQSUB8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Saturating Subtract 8
0x2F009200 uqxtn UQXTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Unsigned Saturating Extract Narrow
0x0E20E800 urecpe URECPE <Vd>.<T>, <Vn>.<T> SIMD Two Register Vector Unsigned Reciprocal Estimate
0x0780F010 usad8 USAD8<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Sum of Absolute Differences
0x07800010 usada8 USADA8<c> <Rd>, <Rn>, <Rm>, <Ra> SIMD Integer Unsigned Sum of Absolute Differences Accumulate
0x06E00010 usat USAT<c> <Rd>, #<imm>, <Rm> {, <shift>} Data Proc Unsigned Saturate (A32)
0x06E00F30 usat16 USAT16<c> <Rd>, #<imm>, <Rm> Data Proc Unsigned Saturate 16 (A32)
0xFC800D00 usdot USDOT<c>.S8 <Qd>, <Qn>, <Qm> NEON 3-Reg Unsigned Signed Dot Product (A32)
0x4E409C00 usdot USDOT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Unsigned-Signed Dot Product (NEON)
0x2F000400 ushr USHR <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Vector Unsigned Shift Right
0x4E40B800 usmmla USMMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> NEON 3-Reg Unsigned-Signed Matrix Multiply-Accumulate (NEON)
0x2F001400 usra USRA <Vd>.<T>, <Vn>.<T>, #<shift> SIMD Shift Imm Unsigned Shift Right and Accumulate
0x06500F70 usub16 USUB16<c> <Rd>, <Rn>, <Rm> SIMD Integer Unsigned Subtract 16 (A32)
0x2E202000 usubl USUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts> SIMD Three Register Diff Unsigned Subtract Long
0x0524A000 uunpkhi UUNPKHI <Zd>.<T>, <Zn>.<Tb> SVE Permute SVE Unsigned Unpack High
0x05248000 uunpklo UUNPKLO <Zd>.<T>, <Zn>.<Tb> SVE Permute SVE Unsigned Unpack Low
0x06E00070 uxtab UXTAB<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Unsigned Extend and Add Byte
0x06C00070 uxtab16 UXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Unsigned Extend and Add Byte 16
0x06F00070 uxtah UXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>} Data Proc Unsigned Extend and Add Halfword
0xB2C0 uxtb UXTB <Rd>, <Rm> Thumb Data Proc Unsigned Extend Byte (Thumb)
0x06EF0070 uxtb UXTB<c> <Rd>, <Rm> {, <rotation>} Data Proc Unsigned Extend Byte (A32)
0x06CF0070 uxtb16 UXTB16<c> <Rd>, <Rm> {, <rotation>} Data Proc Unsigned Extend Byte 16 (A32)
0xB280 uxth UXTH <Rd>, <Rm> Thumb Data Proc Unsigned Extend Halfword (Thumb)
0x06FF0070 uxth UXTH<c> <Rd>, <Rm> {, <rotation>} Data Proc Unsigned Extend Halfword (A32)
0x0E001800 uzp1 UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Unzip 1
0x05320000 uzp1 UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Unzip 1
0x0E005800 uzp2 UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Unzip 2
0x05330000 uzp2 UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Unzip 2
0xF2000710 vaba VABA<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Difference and Accumulate
0xF2800500 vabal VABAL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Absolute Difference and Accumulate Long
0xF2000700 vabd VABD<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Difference
0xF2800700 vabdl VABDL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Absolute Difference Long
0x0EB00BC0 vabs VABS<c>.F64 <Dd>, <Dm> VFP Unary Vector Absolute Value (Double)
0x0EB00AC0 vabs VABS<c>.F32 <Sd>, <Sm> VFP Unary Vector Absolute Value (VFP)
0xF3B10300 vabs VABS<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Absolute Value
0xF3000E10 vacge VACGE<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Compare Greater or Equal
0xF3000E00 vacgt VACGT<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Absolute Compare Greater Than
0x0E300A00 vadd VADD<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Add (VFP)
0x0E300B00 vadd VADD<c>.F64 <Dd>, <Dn>, <Dm> VFP Arith Vector Add Double (VFP)
0xF2000800 vadd VADD<c>.I<size> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Add (Integer)
0xF2800400 vaddhn VADDHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Add High Narrow
0xF2800000 vaddl VADDL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Add Long
0xF2800100 vaddw VADDW<c>.<dt> <Qd>, <Qn>, <Dm> NEON 3-Reg Vector Add Wide
0xF2000110 vand VAND<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Bitwise AND
0xF3B60600 vbfcvt VBFCVT<c>.BF16.F32 <Qd>, <Qm> NEON BFloat16 Vector Convert BFloat16 (A32)
0xFC000D10 vbfdot VBFDOT<c>.BF16 <Qd>, <Qn>, <Qm> NEON BFloat16 Vector BFloat16 Dot Product (A32)
0xFC300C10 vbfmmla VBFMMLA<c>.BF16 <Qd>, <Qn>, <Qm> NEON BFloat16 Vector BFloat16 Matrix Multiply (A32)
0xF2100110 vbic VBIC<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Bitwise Bit Clear
0xF3300110 vbif VBIF<c> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Bit Insert False
0xF3200110 vbit VBIT<c> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Bit Insert True
0xF3100110 vbsl VBSL<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Bit Select
0xFC800840 vcadd VCADD<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> NEON Complex Vector Complex Add (A32)
0xF2000810 vceq VCEQ<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Compare Equal
0xF2000310 vcge VCGE<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Compare Greater Than or Equal
0xF2000300 vcgt VCGT<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Compare Greater Than
0xF2000310 vcle VCLE<c>.<dt> <Qd>, <Qn>, <Qm> NEON Alias Vector Compare Less Than or Equal
0xF3B00200 vcls VCLS<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Count Leading Sign Bits
0xF2000300 vclt VCLT<c>.<dt> <Qd>, <Qn>, <Qm> NEON Alias Vector Compare Less Than
0xF3B00280 vclz VCLZ<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Count Leading Zeros
0xFC800840 vcmla VCMLA<c>.I<size> <Qd>, <Qn>, <Qm>, #<rot> NEON Complex Vector Complex Multiply Accumulate (A32)
0x0EB50A40 vcmp VCMP<c>.F32 <Sd>, #0.0 VFP Compare Vector Compare Zero (VFP)
0x0EB40B40 vcmp VCMP<c>.F64 <Dd>, <Dm> VFP Compare Vector Compare (Double)
0x0EB40A40 vcmp VCMP<c>.F32 <Sd>, <Sm> VFP Compare Vector Compare (VFP)
0x0EB40AC0 vcmpe VCMPE<c>.F32 <Sd>, <Sm> VFP Compare Vector Compare Exception (VFP)
0xF3B00500 vcnt VCNT<c>.8 <Qd>, <Qm> NEON 2-Reg Vector Count Set Bits
0x0EBE0A40 vcvt VCVT<c>.<Td>.<Tm> <Qd>, <Qm>, #<fbits> VFP Convert Vector Convert (Fixed Point)
0x0EBD0AC0 vcvt VCVT<c>.<Td>.<Tm> <Sd>, <Sm> VFP Convert Vector Convert (Float to Integer)
0x0EBC0B40 vcvta VCVTA<c>.<dt>.F64 <Sd>, <Dm> VFP Convert Vector Convert to Integer (Nearest, Double)
0xF3BC0000 vcvta VCVTA<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Nearest)
0xEB20A40 vcvtb VCVTB<c>.F16.F32 <Sd>, <Sm> VFP Convert Vector Convert Half-Precision (Bottom)
0x0EB20A40 vcvtb VCVTB<c>.F16.F32 <Sd>, <Sm> VFP Convert Vector Convert Half-Precision (Bottom)
0xF3BC0180 vcvtm VCVTM<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Minus Infinity)
0x0EBC0B40 vcvtn VCVTN<c>.<dt>.F64 <Sd>, <Dm> VFP Convert Vector Convert to Integer (Nearest Even, Double)
0xF3BC0080 vcvtn VCVTN<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Nearest Even)
0xF3BC0100 vcvtp VCVTP<c>.<dt>.F32 <Qd>, <Qm> NEON 2-Reg Vector Convert to Integer (Plus Infinity)
0xEB20AC0 vcvtt VCVTT<c>.F16.F32 <Sd>, <Sm> VFP Convert Vector Convert Half-Precision (Top)
0x0EB20AC0 vcvtt VCVTT<c>.F16.F32 <Sd>, <Sm> VFP Convert Vector Convert Half-Precision (Top)
0x0E800B00 vdiv VDIV<c>.F64 <Dd>, <Dn>, <Dm> VFP Arith Vector Divide (Double)
0x0E800A00 vdiv VDIV<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Divide (VFP)
0xF3B00C00 vdup VDUP<c>.<dt> <Qd>, <Dm[x]> NEON Scalar Vector Duplicate (Scalar)
0xF3000110 veor VEOR<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Exclusive OR
0xF2B00000 vext VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm> NEON Extract Vector Extract
0x0EA00B00 vfma VFMA<c>.F64 <Qd>, <Qn>, <Qm> VFP Arith Vector Fused Multiply Accumulate (Double)
0xF2000C10 vfma VFMA<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Fused Multiply Accumulate
0x0EA00B40 vfms VFMS<c>.F64 <Qd>, <Qn>, <Qm> VFP Arith Vector Fused Multiply Subtract (Double)
0xF2200C10 vfms VFMS<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Fused Multiply Subtract
0xEE900A00 vfnma VFNMA<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Fused Negated Multiply Accumulate
0xEE900A40 vfnms VFNMS<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Fused Negated Multiply Subtract
0xF2000000 vhadd VHADD<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Halving Add
0xF2000200 vhsub VHSUB<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Halving Subtract
0xEEBE0B40 vjcvt VJCVT<c>.S32.F64 <Sd>, <Dm> VFP Convert Vector Javascript Convert (A32)
0xF4200000 vld1 VLD1<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (Single Element)
0xF4200000 vld2 VLD2<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (2-Element Structure)
0xF4400000 vld3 VLD3<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (3-Element Structure)
0xF4000000 vld4 VLD4<c>.<size> <list>, [<Rn>]{!} NEON Load Vector Load Multiple (4-Element Structure)
0x0C900A00 vldm VLDM<c><mode> <Rn>{!}, <list> VFP Load Multiple Vector Load Multiple (VFP)
0x0D100A00 vldr VLDR<c> <Sd>, [<Rn>, #+/-<imm>] VFP Load Vector Load Register (VFP)
0xF2000600 vmax VMAX<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Maximum
0xF2000F00 vmaxnm VMAXNM<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Maximum Number
0xFE800B00 vmaxnm VMAXNM<c>.F64 <Dd>, <Dn>, <Dm> VFP Misc Vector Maximum Number (Double)
0xF2000610 vmin VMIN<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Minimum
0xF2200F00 vminnm VMINNM<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Minimum Number
0xFE800B40 vminnm VMINNM<c>.F64 <Dd>, <Dn>, <Dm> VFP Misc Vector Minimum Number (Double)
0x0E000A00 vmla VMLA<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Multiply Accumulate (VFP)
0xF2000900 vmla VMLA<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Multiply Accumulate
0x0E000A40 vmls VMLS<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Multiply Subtract (VFP)
0xF2000910 vmls VMLS<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Multiply Subtract
0xFC200C00 vmmla VMMLA<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Matrix Multiply Accumulate (A32)
0x0EB00B40 vmov VMOV<c>.F64 <Dd>, <Dm> VFP Move Vector Move (Double)
0x0C400B10 vmov VMOV<c> <Rt>, <Rt2>, <Dm> VFP Transfer Vector Move (Double <-> 2xGPR)
0x0EB00A40 vmov VMOV<c>.F32 <Sd>, <Sm> VFP Move Vector Move (Register)
0x0E000A10 vmov VMOV<c> <Sn>, <Rt> VFP Transfer Vector Move (Core <-> VFP)
0xF2800010 vmov VMOV<c>.<dt> <Qd>, #<imm> NEON Imm Vector Move (Immediate)
0xF2800A10 vmovl VMOVL<c>.<dt> <Qd>, <Dm> NEON 2-Reg Vector Move Long
0xF3B00200 vmovn VMOVN<c>.<dt> <Dd>, <Qm> NEON 2-Reg Vector Move Narrow
0x0EF10A10 vmrs VMRS<c> <Rt>, <spec_reg> VFP System Move VFP System Register to Register
0x0EE10A10 vmsr VMSR<c> <spec_reg>, <Rt> VFP System Move Register to VFP System Register
0x0E200A00 vmul VMUL<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Multiply (VFP)
0xF2000910 vmul VMUL<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Multiply
0xF2800C00 vmull VMULL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Multiply Long
0xF3B00580 vmvn VMVN<c> <Qd>, <Qm> NEON 2-Reg Vector Move NOT
0x0EB10B40 vneg VNEG<c>.F64 <Dd>, <Dm> VFP Unary Vector Negate (Double)
0x0EB10A40 vneg VNEG<c>.F32 <Sd>, <Sm> VFP Unary Vector Negate (VFP)
0xF3B10380 vneg VNEG<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Negate
0x0E200A40 vnmul VNMUL<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Negated Multiply (VFP)
0xF2200110 vorn VORN<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector OR NOT
0xF2200110 vorr VORR<c> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Logical OR
0xF3B00600 vpadal VPADAL<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Pairwise Add and Accumulate Long
0xF2000B10 vpadd VPADD<c>.<dt> <Dd>, <Dn>, <Dm> NEON 3-Reg Vector Pairwise Add
0xF3B00200 vpaddl VPADDL<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Pairwise Add Long
0xF2000A00 vpmax VPMAX<c>.<dt> <Dd>, <Dn>, <Dm> NEON 3-Reg Vector Pairwise Maximum
0xF2000A10 vpmin VPMIN<c>.<dt> <Dd>, <Dn>, <Dm> NEON 3-Reg Vector Pairwise Minimum
0x0CBD0A00 vpop VPOP <list> VFP Load Multiple Vector Pop (VFP)
0x0D2D0A00 vpush VPUSH <list> VFP Store Multiple Vector Push (VFP)
0xF2000010 vqadd VQADD<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Add
0xF2800900 vqdmlal VQDMLAL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Saturating Doubling Multiply Accumulate Long
0xF2800B00 vqdmlsl VQDMLSL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Saturating Doubling Multiply Subtract Long
0xF2000B00 vqdmulh VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Doubling Multiply High
0xF2800D00 vqdmull VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm> NEON 3-Reg Vector Saturating Doubling Multiply Long
0xF2000B10 vqrdmulh VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Rounding Doubling Multiply High
0xF2000510 vqrshl VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Saturating Rounding Shift Left
0xF2800910 vqrshrn VQRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Saturating Rounding Shift Right Narrow
0xF2000400 vqshl VQSHL<c>.<dt> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Saturating Shift Left (Register)
0xF2800710 vqshl VQSHL<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Left (Immediate)
0xF2800610 vqshlu VQSHLU<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Left Unsigned
0xF2800D10 vqshr VQSHR<c>.U<size> <Qd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Right (Unsigned)
0xF2800910 vqshrn VQSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Saturating Shift Right Narrow
0xF2000210 vqsub VQSUB<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Saturating Subtract
0xF2800410 vraddhn VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Rounding Add High Narrow
0xF3B00400 vrecpe VRECPE<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reciprocal Estimate
0xF2000F10 vrecps VRECPS<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Reciprocal Step
0xF3B00100 vrev16 VREV16<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reverse 16
0xF3B00080 vrev32 VREV32<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reverse 32
0xF3B00000 vrev64 VREV64<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reverse 64
0xF3BA0000 vrinta VRINTA<c>.F32 <Qd>, <Qm> NEON 2-Reg Vector Round Floating-Point (Nearest)
0xEB50AC0 vrintm VRINTM<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Minus Infinity)
0xEB50BC0 vrintm VRINTM<c>.F64 <Dd>, <Dm> VFP Unary Vector Round Floating-Point Double (Minus Infinity)
0xF3BA0080 vrintn VRINTN<c>.F32 <Qd>, <Qm> NEON 2-Reg Vector Round Floating-Point (Nearest Even)
0xEB40AC0 vrintp VRINTP<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Plus Infinity)
0xEB40BC0 vrintp VRINTP<c>.F64 <Dd>, <Dm> VFP Unary Vector Round Floating-Point Double (Plus Infinity)
0xEB60A40 vrintr VRINTR<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Current)
0xEB70A40 vrintx VRINTX<c>.F32 <Sd>, <Sm> VFP Unary Vector Round Floating-Point (Exact)
0xF3BA0180 vrintz VRINTZ<c>.F32 <Qd>, <Qm> NEON 2-Reg Vector Round Floating-Point (Zero)
0xF2000500 vrshl VRSHL<c>.<dt> <Qd>, <Qm>, <Qn> NEON 3-Reg Vector Rounding Shift Left
0xF2800210 vrshr VRSHR<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Rounding Shift Right
0xF2800810 vrshrn VRSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Rounding Shift Right Narrow
0xF3B00480 vrsqrte VRSQRTE<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Reciprocal Square Root Estimate
0xF2200F10 vrsqrts VRSQRTS<c>.F32 <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Reciprocal Square Root Step
0xF2800310 vrsra VRSRA<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Rounding Shift Right and Accumulate
0xF2800610 vrsubhn VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Rounding Subtract High Narrow
0xFE000A00 vsel VSEL<cond>.F32 <Sd>, <Sn>, <Sm> VFP Misc Vector Select
0xFE000B00 vsel VSEL<cond>.F64 <Dd>, <Dn>, <Dm> VFP Misc Vector Select (Double)
0xF2800510 vshl VSHL<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Left (Immediate)
0xF2800010 vshr VSHR<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Right (Immediate)
0xF2800810 vshrn VSHRN<c>.<dt> <Dd>, <Qm>, #<imm> NEON Shift Vector Shift Right Narrow
0xF2800510 vsli VSLI<c>.<size> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Left and Insert
0xFC200C00 vsmmla VSMMLA<c>.S8 <Qd>, <Qn>, <Qm> NEON MatMul Vector Signed Int8 Matrix Multiply (A32)
0x0EB10BC0 vsqrt VSQRT<c>.F64 <Dd>, <Dm> VFP Unary Vector Square Root (Double)
0x0EB10AC0 vsqrt VSQRT<c>.F32 <Sd>, <Sm> VFP Unary Vector Square Root (VFP)
0xF2800110 vsra VSRA<c>.<dt> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Right and Accumulate
0xF2800410 vsri VSRI<c>.<size> <Qd>, <Qm>, #<imm> NEON Shift Vector Shift Right and Insert
0xF4000000 vst1 VST1<c>.<size> <list>, [<Rn>]{!} NEON Store Vector Store Multiple (Single Element)
0xF4400000 vst3 VST3<c>.<size> <list>, [<Rn>]{!} NEON Store Vector Store Multiple (3-Element Structure)
0xF4000000 vst4 VST4<c>.<size> <list>, [<Rn>]{!} NEON Store Vector Store Multiple (4-Element Structure)
0x0C800A00 vstm VSTM<c><mode> <Rn>{!}, <list> VFP Store Multiple Vector Store Multiple (VFP)
0x0D000A00 vstr VSTR<c> <Sd>, [<Rn>, #+/-<imm>] VFP Store Vector Store Register (VFP)
0x0E300A40 vsub VSUB<c>.F32 <Sd>, <Sn>, <Sm> VFP Arith Vector Subtract (VFP)
0xF2000810 vsub VSUB<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Subtract (Integer)
0xF2800600 vsubhn VSUBHN<c>.<dt> <Dd>, <Qn>, <Qm> NEON 3-Reg Vector Subtract High Narrow
0xF3B20000 vswp VSWP<c> <Qd>, <Qm> NEON 2-Reg Vector Swap
0xF3B00800 vtbl VTBL<c>.8 <Dd>, <list>, <Dm> NEON Table Vector Table Lookup
0xF3B00840 vtbx VTBX<c>.8 <Dd>, <list>, <Dm> NEON Table Vector Table Extension
0xF3B00080 vtrn VTRN<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Transpose
0xF2000810 vtst VTST<c>.<dt> <Qd>, <Qn>, <Qm> NEON 3-Reg Vector Test Bits
0xFC200C10 vummla VUMMLA<c>.U8 <Qd>, <Qn>, <Qm> NEON MatMul Vector Unsigned Matrix Multiply (A32)
0xFC800D00 vusdot VUSDOT<c>.S8 <Qd>, <Qn>, <Qm> NEON DotProd Vector Unsigned-Signed Dot Product (A32)
0xFCA00C00 vusmmla VUSMMLA<c>.S8 <Qd>, <Qn>, <Qm> NEON MatMul Vector Unsigned-Signed Matrix Multiply (A32)
0xF3B00100 vuzp VUZP<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Unzip
0xF3B00180 vzip VZIP<c>.<dt> <Qd>, <Qm> NEON 2-Reg Vector Zip
0xD503205F wfe WFE System Alias Wait For Event
0x0320F002 wfe WFE System Hint Wait For Event (A32)
0xBF20 wfe WFE Thumb System Wait For Event (Thumb)
0xD5031000 wfet WFET <Wn> System Wait For Event with Timeout
0xD503207F wfi WFI System Alias Wait For Interrupt
0x0320F003 wfi WFI System Hint Wait For Interrupt (A32)
0xBF30 wfi WFI Thumb System Wait For Interrupt (Thumb)
0xD5031020 wfit WFIT <Wn> System Wait For Interrupt with Timeout
0x25440000 whilehi WHILEHI <Pd>.<T>, <Xn>, <Xm> SVE Compare SVE While Higher (Unsigned)
0x25450000 whilehs WHILEHS <Pd>.<T>, <Xn>, <Xm> SVE Compare SVE While Higher or Same (Unsigned)
0x25402000 whilele WHILELE <Pd>.<T>, <Xn>, <Xm> SVE Compare Scalar SVE While Less Than or Equal
0x25420000 whilelo WHILELO <Pd>.<T>, <Xn>, <Xm> SVE Compare SVE While Lower (Unsigned)
0x25430000 whilels WHILELS <Pd>.<T>, <Xn>, <Xm> SVE Compare SVE While Lower or Same (Unsigned)
0x25400000 whilelt WHILELT <Pd>.<T>, <Xn>, <Xm> SVE Compare Scalar SVE While Less Than
0xDAC603E0 xpacd XPACD <Xd> Data Processing Strip Pointer Authentication Code (Data)
0xDAC403E0 xpaci XPACI <Xd> Data Processing Strip Pointer Authentication Code (Inst)
0xD50320FF xpaclri XPACLRI System Strip PAC from Instruction Address
0x0F001200 xtn XTN <Vd>.<Tb>, <Vn>.<Ta> SIMD Shift Imm Vector Extract Narrow
0xD503203F yield YIELD System Alias Yield
0x0320F001 yield YIELD System Hint Yield (A32)
0xBF10 yield YIELD Thumb System Yield (Thumb)
0x0E003800 zip1 ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Zip 1 (Interleave)
0x05340000 zip1 ZIP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Zip 1
0x0E007800 zip2 ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T> SIMD Permute Vector Zip 2 (Interleave)
0x05350000 zip2 ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T> SVE Permute SVE Zip 2