fneg

Vector Floating-Point Negate

FNEG <Vd>.<T>, <Vn>.<T>

Negates each element.

Details

Inverts the sign bit of each floating-point element in the source vector, placing the negated value in the destination vector. This is a bit-level operation that does not signal floating-point exceptions. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

Pseudocode Operation

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  sign_bit = NOT(Vn[element][element_size-1])
  Vd[element][element_size-1:0] = sign_bit || Vn[element][element_size-2:0]

Example

FNEG v0.4s.T, v1.4s.T

Encoding

Binary Layout
0
Q
1
011101
sz
10000
01111
10
Rn
Rd
 
Format SIMD Two Register
Opcode 0x2EA0F800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2EF8F800 FNEG <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 1 | 111100 | 01111 | 10 | Rn | Rd
0x2EA0F800 FNEG <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 011101 | sz | 10000 | 01111 | 10 | Rn | Rd
0x1EE14000 FNEG <Hd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 10000 | 10 | 10000 | Rn | Rd
0x1E214000 FNEG <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 10000 | 10 | 10000 | Rn | Rd
0x1E614000 FNEG <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 10000 | 10 | 10000 | Rn | Rd
0x041DA000 FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T> A64 00000100 | size | 011 | 10 | 1 | 101 | Pg | Zn | Zd

Description

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    if neg then
        element = FPNeg(element, FPCR);
    else
        element = FPAbs(element, FPCR);
    Elem[result, e, esize] = element;

V[d, datasize] = result;