ldr

Load Register (Literal)

LDR <Wt>, <label>

Loads a word from a PC-relative address.

Pseudocode Operation

address ← PC + (sign_extend(imm19) << 2); Wt ← [address]

Example

LDR w3, label

Encoding

Binary Layout

00

31:30

011

29:27

0

26

00

25:24

imm19

23:5

Rt

4:0

 

Format Load Literal

Opcode 0x18000000

Extension Base

Operands

• Wt
  Transfer 32-bit integer register (load/store)
• label
  Label

Related

Other forms of ldr

• ldr Load SIMD&FP Register (Immediate)
• ldr Load Register (Immediate)
• ldr Load Register (Register)
• ldr Load Register PC-Relative (A32)
• ldr Load Register PC-Relative (Thumb)
• ldr Load Register (A32 Immediate)

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x3C400400	LDR <Bt>, [<Xn|SP>], #<simm>		A64		00 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x7C400400	LDR <Ht>, [<Xn|SP>], #<simm>		A64		01 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xBC400400	LDR <St>, [<Xn|SP>], #<simm>		A64		10 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0xFC400400	LDR <Dt>, [<Xn|SP>], #<simm>		A64		11 | 111 | 1 | 00 | 01 | 0 | imm9 | 01 | Rn | Rt
0x3CC00400	LDR <Qt>, [<Xn|SP>], #<simm>		A64		00 | 111 | 1 | 00 | 11 | 0 | imm9 | 01 | Rn | Rt
0x3C400C00	LDR <Bt>, [<Xn|SP>, #<simm>]!		A64		00 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x7C400C00	LDR <Ht>, [<Xn|SP>, #<simm>]!		A64		01 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xBC400C00	LDR <St>, [<Xn|SP>, #<simm>]!		A64		10 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0xFC400C00	LDR <Dt>, [<Xn|SP>, #<simm>]!		A64		11 | 111 | 1 | 00 | 01 | 0 | imm9 | 11 | Rn | Rt
0x3CC00C00	LDR <Qt>, [<Xn|SP>, #<simm>]!		A64		00 | 111 | 1 | 00 | 11 | 0 | imm9 | 11 | Rn | Rt
0x3D400000	LDR <Bt>, [<Xn|SP>{, #<pimm>}]		A64		00 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0x7D400000	LDR <Ht>, [<Xn|SP>{, #<pimm>}]		A64		01 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xBD400000	LDR <St>, [<Xn|SP>{, #<pimm>}]		A64		10 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt
0xFD400000	LDR <Dt>, [<Xn|SP>{, #<pimm>}]		A64		11 | 111 | 1 | 01 | 01 | imm12 | Rn | Rt

Description

Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address = PC64 + offset;
bits(size*8) data;
boolean privileged = PSTATE.EL != EL0;

AccessDescriptor accdesc = CreateAccDescGPR(memop, FALSE, privileged, FALSE);
case memop of
    when MemOp_LOAD
        data = Mem[address, size, accdesc];
        if signed then
            X[t, 64] = SignExtend(data, 64);
        else
            X[t, size*8] = data;

    when MemOp_PREFETCH
        Prefetch(address, t<4:0>);