uqadd

Vector Unsigned Saturating Add

UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Adds unsigned integers with saturation.

Details

Vector Unsigned Saturating Add adds corresponding unsigned integer elements from two NEON registers with saturation, placing the sum into the destination register. If the sum exceeds the maximum value representable in the element type, the result is saturated to that maximum. This instruction operates element-wise on all vector elements and does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  sum ← Vn[i] + Vm[i]
  if sum > UINT_MAX(size) then
    Vd[i] ← UINT_MAX(size)
  else
    Vd[i] ← sum
  end if
end for

Example

UQADD v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
1
01110
size
1
Rm
00001
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x2E200C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E200C00 UQADD <V><d>, <V><n>, <V><m> A64 01 | 1 | 11110 | size | 1 | Rm | 00001 | 1 | Rn | Rd
0x2E200C00 UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 00001 | 1 | Rn | Rd
0x44198000 UQADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01000100 | size | 011 | 0 | 0 | 1 | 100 | Pg | Zm | Zdn
0x2525C000 UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>} A64 00100101 | size | 100 | 10 | 1 | 11 | sh | imm8 | Zdn
0x04201400 UQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 00000100 | size | 1 | Zm | 000 | 10 | 1 | Zn | Zd

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d, datasize] = result;