vraddhn

Vector Rounding Add High Narrow

VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm>

Adds wide elements, rounds, and returns high narrow half.

Pseudocode Operation

for i = 0 to (128 / (esize * 2) - 1)
  sum ← Qn[i] + Qm[i]
  rounded ← sum + (1 << (esize - 1))
  Dd[i] ← (rounded >> esize)[esize - 1:0]

Example

VRADDHN.dt d0, q1, q2

Encoding

Binary Layout

1111001

31:25

1

24

1

23

D

22

size

21:20

Vn

19:16

Vd

15:12

0100

11:8

N

7

0

6

M

5

0

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF3800400

Extension NEON (SIMD)

Operands

• Dd
  Dest Narrow
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3800400	VRADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>		A32		1111001 | 1 | 1 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm
0xFF800400	VRADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>		T32		111 | 1 | 11111 | D | size | Vn | Vd | 0100 | N | 0 | M | 0 | Vm

Description

Vector Rounding Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and places the most significant half of each result in a doubleword vector. The results are rounded. For truncated results, see VADDHN. The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    round_const = 1 << (esize-1);
    for e = 0 to elements-1
        result = Elem[Qin[n>>1],e,2*esize] + Elem[Qin[m>>1],e,2*esize] + round_const;
        Elem[D[d],e,esize] = result<2*esize-1:esize>;