stur

Store Register (Unscaled)

STUR <Wt>, [<Xn|SP>, #<simm>]

Stores a register using an unscaled immediate offset.

Pseudocode Operation

address ← Xn + SignExtend(imm9, 64)
[address, 4] ← Wt[31:0]

Example

STUR w3, [x1, #-8]

Encoding

Binary Layout
10
31:30
111
29:27
0
26
00
25:24
00
23:22
0
21
imm9
20:12
00
11:10
Rn
9:5
Rt
4:0
 
Format Load/Store
Opcode 0xB8000000
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • simm
    Signed immediate offset

Related

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x3C000000 STUR <Bt>, [<Xn|SP>{, #<simm>}] A64 00 | 111 | 1 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt
0x7C000000 STUR <Ht>, [<Xn|SP>{, #<simm>}] A64 01 | 111 | 1 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt
0xBC000000 STUR <St>, [<Xn|SP>{, #<simm>}] A64 10 | 111 | 1 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt
0xFC000000 STUR <Dt>, [<Xn|SP>{, #<simm>}] A64 11 | 111 | 1 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt
0x3C800000 STUR <Qt>, [<Xn|SP>{, #<simm>}] A64 00 | 111 | 1 | 00 | 10 | 0 | imm9 | 00 | Rn | Rt
0xB8000000 STUR <Wt>, [<Xn|SP>{, #<simm>}] A64 10 | 111 | 0 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt
0xF8000000 STUR <Xt>, [<Xn|SP>{, #<simm>}] A64 11 | 111 | 0 | 00 | 00 | 0 | imm9 | 00 | Rn | Rt

Description

Store Register (unscaled) calculates an address from a base register value and an immediate offset, and stores a 32-bit word or a 64-bit doubleword to the calculated address, from a register. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = X[t, datasize];
Mem[address, datasize DIV 8, accdesc] = data;