sxtah

Signed Extend and Add Halfword

SXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>}

Sign-extends a halfword and adds to Rn.

Details

Sign-extends the least significant halfword of Rm (optionally rotated), adds it to Rn, and writes the result to Rd. This is an A32 instruction that operates on general-purpose registers and does not affect the condition flags. The rotation parameter is optional (ROR by 0, 8, 16, or 24 bits before sign-extension).

Pseudocode Operation

rotated ← ROR(Rm, rotation)
halfword_value ← rotated[15:0]
sign_extended ← SignExtend(halfword_value, 32)
Rd ← Rn + sign_extended

Example

SXTAH r0, r1, r2

Encoding

Binary Layout
cond
01101
0
11
Rn
Rd
rotate
0
0
0111
Rm
 
Format Data Proc
Opcode 0x06B00070
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    Accumulator
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06B00070 SXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>} A32 cond | 01101 | 0 | 11 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm
0xFA00F080 SXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>} T32 111110100 | 00 | 0 | Rn | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Signed Extend and Add Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = R[n] + SignExtend(rotated<15:0>, 32);