mrrc

Move to Two Registers from Coprocessor (A32)

MRRC<c> <coproc>, <opc1>, <Rt>, <Rt2>, <CRm>

Reads a coprocessor register into two general-purpose registers.

Details

Moves data from a coprocessor into two consecutive general-purpose registers (64-bit data transfer). The instruction is conditional and executes only if the condition code is satisfied. No ARM condition flags are modified by this instruction itself, though the coprocessor may affect them. This is an A32-only instruction; the 64-bit result is split with Rt receiving the lower 32 bits and Rt2 the upper 32 bits.

Pseudocode Operation

if ConditionPassed(cond) then
  data64 ← CP64[coproc, opc1, CRm]
  Rt ← data64[31:0]
  Rt2 ← data64[63:32]

Example

MRRC p15, 0, r3, r4, c2

Encoding

Binary Layout
cond
11000
1
0
1
Rt2
Rt
111
coproc<0>
opc1
CRm
 
Format Coprocessor
Opcode 0x0C500E00
Extension A32 (System)

Operands

  • coproc
    CP Num
  • Rt
    Dest 1
  • Rt2
    Dest 2

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0C500E00 MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> A32 cond | 11000 | 1 | 0 | 1 | Rt2 | Rt | 111 | coproc<0> | opc1 | CRm
0xEC500E00 MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> T32 111011000 | 1 | 0 | 1 | Rt2 | Rt | 111 | coproc<0> | opc1 | CRm

Description

Move to two general-purpose registers from System register. This instruction copies the value of a System register to two general-purpose registers. The System register descriptions identify valid encodings for this instruction. Other encodings are undefined. For more information see About the AArch32 System register interface and General behavior of System registers. In an implementation that includes EL2, MRRC accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2 configurable instruction enables, disables, and traps. Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    AArch32.SysRegRead64(cp, ThisInstr(), t, t2);