smaxv

Vector Signed Maximum Across

SMAXV <V><d>, <Vn>.<T>

Finds the maximum signed value across the vector.

Pseudocode Operation

result ← Vn[0]
for i = 1 to elements_in_vector - 1
  result ← max_signed(result, Vn[i])
Vd[result_element_index] ← result
Vd[upper_bits] ← 0

Example

SMAXV Vd, v1.4s.T

Encoding

Binary Layout

01110

28:24

size

23:22

11000

21:17

101010

15:10

9:5

4:0

Format SIMD Across Lane

Opcode 0x0E30A800

Extension NEON (SIMD)

Operands

Vd
Dest Scalar
Vn
Src Vector

Other forms of smaxv

smaxv SVE Signed Maximum Reduction

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0E30A800	SMAXV <V><d>, <Vn>.<T>		A64		0 \| Q \| 0 \| 01110 \| size \| 11000 \| 0 \| 101010 \| Rn \| Rd
0x04082000	SMAXV <V><d>, <Pg>, <Zn>.<T>		A64		00000100 \| size \| 0010 \| 0 \| 0 \| 001 \| Pg \| Zn \| Vd

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
integer maxmin;
integer element;

maxmin = Int(Elem[operand, 0, esize], unsigned);
for e = 1 to elements-1
    element = Int(Elem[operand, e, esize], unsigned);
    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);

V[d, esize] = maxmin<esize-1:0>;