vrinta

Vector Round Floating-Point (Nearest)

VRINTA<c>.F32 <Qd>, <Qm>

Rounds float to integral float (Nearest).

Details

Rounds each 32-bit floating-point element in the source vector to the nearest integer value, using round-to-nearest (ties away from zero) rounding mode, and writes the result as a floating-point value to the destination vector. This instruction does not modify the condition flags. Available in A32/T32 with NEON extension.

Pseudocode Operation

for i = 0 to 3
  Qd[i] ← RoundToNearest(Qm[i])
end for

Example

VRINTA.F32 q0, q2

Encoding

Binary Layout
111111101
D
111
0
00
Vd
10
10
0
1
M
0
Vm
 
Format NEON 2-Reg
Opcode 0xFEB80A40
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B20500 VRINTA{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 1 | 010 | 0 | M | 0 | Vm
0xF3B20540 VRINTA{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 1 | 010 | 1 | M | 0 | Vm
0xFFB20500 VRINTA{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 1 | 010 | 0 | M | 0 | Vm
0xFFB20540 VRINTA{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 1 | 010 | 1 | M | 0 | Vm
0xFEB80940 VRINTA{<q>}.F16 <Sd>, <Sm> A32 111111101 | D | 111 | 0 | 00 | Vd | 10 | 01 | 0 | 1 | M | 0 | Vm
0xFEB80A40 VRINTA{<q>}.F32 <Sd>, <Sm> A32 111111101 | D | 111 | 0 | 00 | Vd | 10 | 10 | 0 | 1 | M | 0 | Vm
0xFEB80B40 VRINTA{<q>}.F64 <Dd>, <Dm> A32 111111101 | D | 111 | 0 | 00 | Vd | 10 | 11 | 0 | 1 | M | 0 | Vm

Description

Round floating-point to integer to Nearest with Ties to Away rounds a floating-point value to an integral floating-point value of the same size using the Round to Nearest with Ties to Away rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

Operation

EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
    when 16
        S[d] = Zeros(16) : FPRoundInt(S[m]<15:0>, FPSCR[], rounding, exact);
    when 32
        S[d] = FPRoundInt(S[m], FPSCR[], rounding, exact);
    when 64
        D[d] = FPRoundInt(D[m], FPSCR[], rounding, exact);