vqdmlal

Vector Saturating Doubling Multiply Accumulate Long

VQDMLAL<c>.<dt> <Qd>, <Dn>, <Dm>

Multiplies, doubles, saturates, and adds to accumulator (High precision DSP).

Pseudocode Operation

for i = 0 to (64 / esize - 1)
  product ← Dn[i] * Dm[i]
  doubled ← SatMul(product, 2)  ; saturating double
  Qd[i] ← SatAdd(Qd[i], doubled)

Example

VQDMLAL.dt q0, d1, d2

Encoding

Binary Layout
1111001
31:25
0
24
1
23
D
22
size
21:20
Vn
19:16
Vd
15:12
10
11:10
0
9
1
8
N
7
0
6
M
5
0
4
Vm
3:0
 
Format NEON 3-Reg
Opcode 0xF2800900
Extension NEON (SIMD)

Operands

  • Qd
    Dest Wide
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800900 VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> A32 1111001 | 0 | 1 | D | size | Vn | Vd | 10 | 0 | 1 | N | 0 | M | 0 | Vm
0xF2800340 VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>] A32 1111001 | 0 | 1 | D | size | Vn | Vd | 0 | 0 | 11 | N | 1 | M | 0 | Vm
0xEF800900 VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm> T32 111 | 0 | 11111 | D | size | Vn | Vd | 10 | 0 | 1 | N | 0 | M | 0 | Vm
0xEF800340 VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>] T32 111 | 0 | 11111 | D | size | Vn | Vd | 0 | 0 | 11 | N | 1 | M | 0 | Vm

Description

Vector Saturating Doubling Multiply Accumulate Long multiplies corresponding elements in two doubleword vectors, doubles the products, and accumulates the results into the elements of a quadword vector. The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD scalars. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    integer op2;
    if scalar_form then op2 = SInt(Elem[Din[m],index,esize]);
    for e = 0 to elements-1
        if !scalar_form then op2 = SInt(Elem[Din[m],e,esize]);
        op1 = SInt(Elem[Din[n],e,esize]);
        // The following only saturates if both op1 and op2 equal -(2^(esize-1))
        (product, sat1) = SignedSatQ(2*op1*op2, 2*esize);
        integer result;
        if add then
            result = SInt(Elem[Qin[d>>1],e,2*esize]) + SInt(product);
        else
            result = SInt(Elem[Qin[d>>1],e,2*esize]) - SInt(product);
        boolean sat2;
        (Elem[Q[d>>1],e,2*esize], sat2) = SignedSatQ(result, 2*esize);
        if sat1 || sat2 then FPSCR.QC = '1';