smulwb
Signed Multiply (Word x Bottom)
SMULWB<c> <Rd>, <Rn>, <Rm>
Multiplies 32-bit Rn by bottom 16-bits of Rm, takes top 32-bits of result.
Pseudocode Operation
product ← SignExtend(Rn[31:0], 48) * SignExtend(Rm[15:0], 48);
Rd ← product[47:16];Example
SMULWB r0, r1, r2
Encoding
Binary Layout
cond
31:28
00010
27:23
01
22:21
0
20
Rd
19:16
0000
15:12
Rm
11:8
1
7
0
6
1
5
0
4
Rn
3:0
Operands
-
Rd
Destination general-purpose register -
Rn
Word Src -
Rm
Half Src
Related
More in A32 (DSP)
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x012000A0 | SMULWB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> | A32 | cond | 00010 | 01 | 0 | Rd | 0000 | Rm | 1 | 0 | 1 | 0 | Rn | ||
| 0xFB30F000 | SMULWB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> | T32 | 111110110 | 011 | Rn | 1111 | Rd | 00 | 0 | 0 | Rm |
Description
Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
product = SInt(R[n]) * SInt(operand2);
R[d] = product<47:16>;
// Signed overflow cannot occur