vhsub

Vector Halving Subtract

VHSUB<c>.<dt> <Qd>, <Qn>, <Qm>

Subtract elements and shift right by 1.

Pseudocode Operation

for each lane i of size specified by dt
  diff ← Qn[i] - Qm[i]
  Qd[i] ← diff >> 1

Example

VHSUB.dt q0, q1, q2

Encoding

Binary Layout

1111001

31:25

U

24

0

23

D

22

size

21:20

Vn

19:16

Vd

15:12

00

11:10

1

9

0

8

N

7

0

6

M

5

0

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF2000200

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2000200	VHSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		A32		1111001 | U | 0 | D | size | Vn | Vd | 00 | 1 | 0 | N | 0 | M | 0 | Vm
0xF2000240	VHSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		A32		1111001 | U | 0 | D | size | Vn | Vd | 00 | 1 | 0 | N | 1 | M | 0 | Vm
0xEF000200	VHSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>		T32		111 | U | 11110 | D | size | Vn | Vd | 00 | 1 | 0 | N | 0 | M | 0 | Vm
0xEF000240	VHSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>		T32		111 | U | 11110 | D | size | Vn | Vd | 00 | 1 | 0 | N | 1 | M | 0 | Vm

Description

Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of the first operand, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated. There is no rounding version. The operand and result elements are all the same type, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Int(Elem[D[n+r],e,esize], unsigned);
            op2 = Int(Elem[D[m+r],e,esize], unsigned);
            result = (if add then op1+op2 else op1-op2) >> 1;
            Elem[D[d+r],e,esize] = result<esize-1:0>;