vhsub

Vector Halving Subtract

VHSUB<c>.<dt> <Qd>, <Qn>, <Qm>

Subtract elements and shift right by 1.

Details

Subtracts corresponding elements of two 128-bit NEON vectors and right-shifts the result by 1 bit (rounded toward zero). The operation is performed element-wise according to the data type. No condition flags are affected. This is an ARMv7 Advanced SIMD instruction, executable in both A32 and T32 states.

Pseudocode Operation

for each lane i of size specified by dt
  diff ← Qn[i] - Qm[i]
  Qd[i] ← diff >> 1

Example

VHSUB.dt q0, q1, q2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
00
1
0
N
0
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2000200
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2000200 VHSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 00 | 1 | 0 | N | 0 | M | 0 | Vm
0xF2000240 VHSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | U | 0 | D | size | Vn | Vd | 00 | 1 | 0 | N | 1 | M | 0 | Vm
0xEF000200 VHSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 00 | 1 | 0 | N | 0 | M | 0 | Vm
0xEF000240 VHSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | U | 11110 | D | size | Vn | Vd | 00 | 1 | 0 | N | 1 | M | 0 | Vm

Description

Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of the first operand, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated. There is no rounding version. The operand and result elements are all the same type, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Int(Elem[D[n+r],e,esize], unsigned);
            op2 = Int(Elem[D[m+r],e,esize], unsigned);
            result = (if add then op1+op2 else op1-op2) >> 1;
            Elem[D[d+r],e,esize] = result<esize-1:0>;