fcadd

Floating-Point Complex Add (NEON)

FCADD <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot>

Complex addition with rotation (NEON).

Pseudocode Operation

if rot == 0 then
  rotated_angle ← 90°
else
  rotated_angle ← 270°
endif
for i = 0 to 3 step 2
  real_acc ← Vn.S[i]
  imag_acc ← Vn.S[i+1]
  real_op ← Vm.S[i]
  imag_op ← Vm.S[i+1]
  (rotated_real, rotated_imag) ← ComplexRotate(real_op, imag_op, rotated_angle)
  Vd.S[i] ← real_acc + rotated_real
  Vd.S[i+1] ← imag_acc + rotated_imag
endfor

Example

FCADD v0.4s.4S, v1.4s.4S, v2.4s.4S, #rot

Encoding

Binary Layout
0
31
Q
30
1
29
01110
28:24
size
23:22
0
21
Rm
20:16
111
15:13
rot
12
01
11:10
Rn
9:5
Rd
4:0
 
Format NEON Complex
Opcode 0x2E00E400
Extension FEAT_FCMA

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register
  • rot
    Rot

Related

Other forms of fcadd

  • fcadd SVE Floating-Point Complex Add

More in FEAT_FCMA

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E00E400 FCADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<rotate> A64 0 | Q | 1 | 01110 | size | 0 | Rm | 111 | rot | 01 | Rn | Rd
0x64008000 FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const> A64 01100100 | size | 00000 | rot | 100 | Pg | Zm | Zdn

Description

Floating-point Complex Add. This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers: This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element3;

for e = 0 to (elements DIV 2)-1
    case rot of
        when '0'
            element1 = FPNeg(Elem[operand2, e*2+1, esize], FPCR);
            element3 = Elem[operand2, e*2, esize];
        when '1'
            element1 = Elem[operand2, e*2+1, esize];
            element3 = FPNeg(Elem[operand2, e*2, esize], FPCR);
    Elem[result, e*2, esize] = FPAdd(Elem[operand1, e*2, esize], element1, FPCR);
    Elem[result, e*2+1, esize] = FPAdd(Elem[operand1, e*2+1, esize], element3, FPCR);

V[d, datasize] = result;