fmla

Floating-Point Multiply Accumulate (Half-Precision)

FMLA <Vd>.8H, <Vn>.8H, <Vm>.8H

Fused multiply-add on half-precision vectors.

Details

The Floating-Point Multiply Accumulate instruction fused multiply-add on half-precision vectors.

Pseudocode Operation

// Fused multiply-add on half-precision vectors

Example

FMLA v0.4s.8H, v1.4s.8H, v2.4s.8H

Encoding

Binary Layout
01001110
010
11111
00010
Vm
Vn
Vd
 
Format NEON FP16
Opcode 0x4E20CC00
Extension FEAT_FP16 (NEON)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register