fabs

Floating-Point Absolute Value (Scalar)

FABS <Hd|Sd|Dd>, <Hn|Sn|Dn>

Calculates the absolute value of a float.

Details

Computes the absolute value of a scalar floating-point operand, clearing the sign bit while preserving all other bits. Floating-point exception conditions (invalid operation, etc.) are not generated. The instruction operates on Half-precision (16-bit), Single-precision (32-bit), or Double-precision (64-bit) formats, determined by the type field. This is an AArch64-only instruction.

Pseudocode Operation

Rd ← abs(Rn)
if (type == 00) then Rd is H-register (16-bit)
else if (type == 01) then Rd is S-register (32-bit)
else if (type == 10) then Rd is D-register (64-bit)

Example

FABS Dd, Dn

Encoding

Binary Layout

11110

10000

Format FP Data Processing

Opcode 0x1E20C000

Extension Floating Point

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x0EF8F800	FABS <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 0 \| 01110 \| 1 \| 111100 \| 01111 \| 10 \| Rn \| Rd
0x0EA0F800	FABS <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 0 \| 011101 \| sz \| 10000 \| 01111 \| 10 \| Rn \| Rd
0x1EE0C000	FABS <Hd>, <Hn>	A64	0 \| 0 \| 0 \| 11110 \| 11 \| 10000 \| 01 \| 10000 \| Rn \| Rd
0x1E20C000	FABS <Sd>, <Sn>	A64	0 \| 0 \| 0 \| 11110 \| 00 \| 10000 \| 01 \| 10000 \| Rn \| Rd
0x1E60C000	FABS <Dd>, <Dn>	A64	0 \| 0 \| 0 \| 11110 \| 01 \| 10000 \| 01 \| 10000 \| Rn \| Rd
0x041CA000	FABS <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	00000100 \| size \| 011 \| 10 \| 0 \| 101 \| Pg \| Zn \| Zd

Description

Floating-point Absolute value (scalar). This instruction calculates the absolute value in the SIMD&FP source register and writes the result to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else 0<127:0>;

bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPAbs(operand, FPCR);
V[d, 128] = result;