irg

Insert Random Tag

IRG <Xd|SP>, <Xn|SP>{, <Xm>}

Inserts a random Allocation Tag into a pointer (MTE).

Pseudocode Operation

if Xm is not present then
  exclude_mask ← 0x0000000000000000
else
  exclude_mask ← Xm
tag ← random_tag_not_in(exclude_mask)
Xd ← (Xn & ~0xF000000000000000) | (tag << 56)

Example

IRG x0, x1

Encoding

Binary Layout

11010110

28:21

20:16

000100

15:10

9:5

4:0

Format Data Processing

Opcode 0x9AC01000

Extension MTE (Memory Tagging)

Operands

Xd
Dest Ptr
Xn
Src Ptr
Xm
Exclude Mask

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x9AC01000	IRG <Xd\|SP>, <Xn\|SP>{, <Xm>}		A64		1 \| 0 \| 0 \| 11010110 \| Xm \| 000100 \| Xn \| Xd

Description

Insert Random Tag inserts a random Logical Address Tag into the address in the first source register, and writes the result to the destination register. Any tags specified in the optional second source register or in GCR_EL1.Exclude are excluded from the selection of the random Logical Address Tag.

Operation

bits(64) operand = if n == 31 then SP[] else X[n, 64];
bits(64) exclude_reg = X[m, 64];
bits(16) exclude = exclude_reg<15:0> OR GCR_EL1.Exclude;
bits(4) rtag;

if AArch64.AllocationTagAccessIsEnabled(PSTATE.EL) then
    if GCR_EL1.RRND == '1' then
        if IsOnes(exclude) then
            rtag = '0000';
        else
            rtag = ChooseRandomNonExcludedTag(exclude);
    else
        bits(4) start_tag = RGSR_EL1.TAG;
        bits(4) offset = AArch64.RandomTag();

        rtag = AArch64.ChooseNonExcludedTag(start_tag, offset, exclude);

        RGSR_EL1.TAG = rtag;
else
    rtag = '0000';

bits(64) result = AArch64.AddressWithAllocationTag(operand, rtag);

if d == 31 then
    SP[] = result;
else
    X[d, 64] = result;

irg