ext

SVE Extract Vector

EXT <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm>

Extracts a vector from a pair (sliding window) using immediate byte index.

Details

Extracts a contiguous sequence of bytes from the concatenation of two SVE vectors (the low vector followed by the high vector) starting at a byte offset, and places the result in the destination vector. This instruction operates only in AArch64 state and does not modify the condition flags.

Pseudocode Operation

offset ← imm
result ← Concatenate(Zdn, Zm)[offset:offset + (VL/8) - 1]
Zdn ← result

Example

EXT z0.s.T, z0.s.T, z2.s.T, #16

Encoding

Binary Layout
00000101001
imm8h
000
imm8l
Zm
Zdn
 
Format SVE Permute
Opcode 0x05200000
Extension SVE

Operands

  • Zdn
    Dest/Low
  • Zm
    High
  • imm
    Index

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E000000 EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> A64 0 | Q | 101110 | 00 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd
0x05600000 EXT <Zd>.B, { <Zn1>.B, <Zn2>.B }, #<imm> A64 00000101011 | imm8h | 000 | imm8l | Zn | Zd
0x05200000 EXT <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm> A64 00000101001 | imm8h | 000 | imm8l | Zm | Zdn

Description

Copy the indexed byte up to the last byte of the first source vector to the bottom of the result vector, then fill the remainder of the result starting from the first byte of the second source vector. The result is placed destructively in the destination and first source vector, or constructively in the destination vector. This instruction is unpredicated. An index that is greater than or equal to the vector length in bytes is treated as zero, resulting in the first source vector being copied to the result unchanged. The Destructive encoding of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is UNPREDICTABLE: The MOVPRFX instruction must be unpredicated. The MOVPRFX instruction must specify the same destination register as this instruction. The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[s1, VL];
bits(VL) operand2 = Z[s2, VL];
bits(VL) result;

bits(VL*2) concat = operand2 : operand1;

if position >= VL then
    result = concat<VL-1:0>;
else
    result = concat<(position+VL)-1:position>;

Z[dst, VL] = result;