smin
Vector Signed Minimum
SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
Returns smaller signed integer per element.
Pseudocode Operation
element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
Vd.<element_size>[i] ← min_signed(Vn.<element_size>[i], Vm.<element_size>[i]);Example
SMIN v0.4s.T, v1.4s.T, v2.4s.T
Encoding
Binary Layout
0
31
Q
30
0
29
01110
28:24
size
23:22
1
21
Rm
20:16
0110
15:12
1
11
1
10
Rn
9:5
Rd
4:0
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0E206C00 | SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | size | 1 | Rm | 0110 | 1 | 1 | Rn | Rd | ||
| 0x11C80000 | SMIN <Wd>, <Wn>, #<simm> | A64 | 0 | 0 | 0 | 1000111 | 0010 | imm8 | Rn | Rd | ||
| 0x91C80000 | SMIN <Xd>, <Xn>, #<simm> | A64 | 1 | 0 | 0 | 1000111 | 0010 | imm8 | Rn | Rd | ||
| 0xC120A020 | SMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101000 | 0000 | 1 | Zdn | 0 | ||
| 0xC120A820 | SMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101010 | 0000 | 1 | Zdn | 0 | 0 | ||
| 0xC120B020 | SMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } | A64 | 11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 1 | Zdn | 0 | ||
| 0xC120B820 | SMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } | A64 | 11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 1 | Zdn | 0 | 0 | ||
| 0x1AC06800 | SMIN <Wd>, <Wn>, <Wm> | A64 | 0 | 0 | 0 | 11010110 | Rm | 011010 | Rn | Rd | ||
| 0x9AC06800 | SMIN <Xd>, <Xn>, <Xm> | A64 | 1 | 0 | 0 | 11010110 | Rm | 011010 | Rn | Rd | ||
| 0x040A0000 | SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 001 | 0 | 1 | 0 | 000 | Pg | Zm | Zdn | ||
| 0x252AC000 | SMIN <Zdn>.<T>, <Zdn>.<T>, #<imm> | A64 | 00100101 | size | 101 | 01 | 0 | 11 | 0 | imm8 | Zdn |
Description
Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer maxmin;
for e = 0 to elements-1
element1 = Int(Elem[operand1, e, esize], unsigned);
element2 = Int(Elem[operand2, e, esize], unsigned);
maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
Elem[result, e, esize] = maxmin<esize-1:0>;
V[d, datasize] = result;