smin

Vector Signed Minimum

SMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Returns smaller signed integer per element.

Details

The Vector Signed Minimum instruction returns smaller signed integer per element.

Pseudocode Operation

Vd ← min(Vn, Vm)

Example

SMIN v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
size
01101
Rm
0100
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E206800
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register