fmadd

Floating-Point Fused Multiply-Add (Scalar)

FMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da>

Calculates (Vn * Vm) + Va without intermediate rounding.

Details

The Floating-Point Fused Multiply-Add instruction calculates (Vn * Vm) + Va without intermediate rounding.

Pseudocode Operation

Vd ← Vn + Vm
// Flags affected: N, Z, C, V

Example

FMADD Dd, Dn, Dm, Da

Encoding

Binary Layout
00011111
type
Rm
0
Ra
Rn
Rd
 
Format FP Data Processing
Opcode 0x1F000000
Extension Floating Point

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register
  • Va
    Addend