splice

SVE Splice Vectors

SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>

Splices two vectors based on the last active element of the first.

Details

SVE Splice Vectors concatenates Zdn and Zm, then extracts a contiguous segment starting from the element position immediately after the last active element in Zdn (as determined by Pg), storing the result back in Zdn. This is used to splice vector sequences. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

Pseudocode Operation

integer esize = 8 << UInt(sz);
integer elements = VL / esize;
integer last_active = -1;
for e = 0 to elements-1
  if Pg[e] == '1' then
    last_active = e;
integer start_pos = last_active + 1;
for e = 0 to elements-1
  if (start_pos + e) < elements then
    Zdn[e * esize +: esize] = Zdn[(start_pos + e) * esize +: esize];
  else
    Zdn[e * esize +: esize] = Zm[(start_pos + e - elements) * esize +: esize];

Example

SPLICE z0.s.T, p0/m, z0.s.T, z2.s.T

Encoding

Binary Layout
00000101
size
101100100
Pv
Zm
Zdn
 
Format SVE Permute
Opcode 0x052C8000
Extension SVE

Operands

  • Zdn
    Dest/First
  • Pg
    Predicate
  • Zm
    Second

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x052D8000 SPLICE <Zd>.<T>, <Pv>, { <Zn1>.<T>, <Zn2>.<T> } A64 00000101 | size | 101101100 | Pv | Zn | Zd
0x052C8000 SPLICE <Zdn>.<T>, <Pv>, <Zdn>.<T>, <Zm>.<T> A64 00000101 | size | 101100100 | Pv | Zm | Zdn

Description

Select a region from the first source vector and copy it to the lowest-numbered elements of the result. Then set any remaining elements of the result to a copy of the lowest-numbered elements from the second source vector. The region is selected using the first and last true elements in the vector select predicate register. The result is placed destructively in the destination and first source vector, or constructively in the destination vector. The Destructive encoding of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is UNPREDICTABLE: The MOVPRFX instruction must be unpredicated. The MOVPRFX instruction must specify the same destination register as this instruction. The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[v, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[s1, VL] else Zeros(VL);
bits(VL) operand2 = Z[s2, VL];
bits(VL) result;
integer x = 0;
boolean active = FALSE;
constant integer lastnum = LastActiveElement(mask, esize);

if lastnum >= 0 then
    for e = 0 to lastnum
        active = active || ActivePredicateElement(mask, e, esize);
        if active then
            Elem[result, x, esize] = Elem[operand1, e, esize];
            x = x + 1;

constant integer nelements = (elements - x) - 1;
for e = 0 to nelements
    Elem[result, x, esize] = Elem[operand2, e, esize];
    x = x + 1;

Z[dst, VL] = result;