ld1r

Load Single Element Replicate

LD1R { <Vt>.<T> }, [<Xn|SP>]

Loads one element and replicates it to all lanes of the vector.

Pseudocode Operation

address ← Xn|SP
element_size ← size_from_T
element ← mem[address]
if Q == 1 then
  lanes ← 16 / element_size
else
  lanes ← 8 / element_size
for i = 0 to lanes - 1 do
  Vt[i] ← element
Xn|SP ← (post-index mode) ? Xn|SP + element_size : Xn|SP

Example

LD1R [x1]

Encoding

Binary Layout
0
31
Q
30
0011010
29:23
1
22
0
21
0000
20:17
0
16
110
15:13
0
12
size
11:10
Rn
9:5
Rt
4:0
 
Format SIMD Load/Store
Opcode 0x0D40C000
Extension NEON (SIMD)

Operands

  • Vt
    Transfer SIMD/FP vector register (load/store)
  • Xn
    First source / base 64-bit integer register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0D40C000 LD1R { <Vt>.<T> }, [<Xn|SP>] A64 0 | Q | 0011010 | 1 | 0 | 0000 | 0 | 110 | 0 | size | Rn | Rt
0x0DDFC000 LD1R { <Vt>.<T> }, [<Xn|SP>], <imm> A64 0 | Q | 0011011 | 1 | 0 | 11111 | 110 | 0 | size | Rn | Rt
0x0DC0C000 LD1R { <Vt>.<T> }, [<Xn|SP>], <Xm> A64 0 | Q | 0011011 | 1 | 0 | Rm | 110 | 0 | size | Rn | Rt

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();

bits(64) address;
bits(64) eaddr;
bits(64) offs;
bits(128) rval;
bits(esize) element;
constant integer ebytes = esize DIV 8;

AccessDescriptor accdesc = CreateAccDescASIMD(memop, nontemporal, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

offs = Zeros(64);
if replicate then
    // load and replicate to all elements
    for s = 0 to selem-1
        eaddr = GenerateAddress(address, offs, accdesc);
        element = Mem[eaddr, ebytes, accdesc];
        // replicate to fill 128- or 64-bit register
        V[t, datasize] = Replicate(element, datasize DIV esize);
        offs = offs + ebytes;
        t = (t + 1) MOD 32;
else
    // load/store one element per register
    for s = 0 to selem-1
        rval = V[t, 128];
        eaddr = GenerateAddress(address, offs, accdesc);
        if memop == MemOp_LOAD then
            // insert into one lane of 128-bit register
            Elem[rval, index, esize] = Mem[eaddr, ebytes, accdesc];
            V[t, 128] = rval;
        else // memop == MemOp_STORE
            // extract from one lane of 128-bit register
            Mem[eaddr, ebytes, accdesc] = Elem[rval, index, esize];
        offs = offs + ebytes;
        t = (t + 1) MOD 32;

if wback then
    if m != 31 then
        offs = X[m, 64];
    address = GenerateAddress(address, offs, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;