br

Branch to Register

BR <Xn>

Indirect branch to address in Xn.

Pseudocode Operation

PC ← Xn

Example

BR x1

Encoding

Binary Layout

1101011

31:25

0

24

0

23

00

22:21

11111

20:16

0000

15:12

0

11

0

10

Rn

9:5

00000

4:0

 

Format Branch (Reg)

Opcode 0xD61F0000

Extension Base

Operands

• Xn
  Target Address

Related

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xD61F0000	BR <Xn>		A64		1101011 | 0 | 0 | 00 | 11111 | 0000 | 0 | 0 | Rn | 00000

Description

Branch to Register branches unconditionally to an address in a register, with a hint that this is not a subroutine return.

Operation

bits(64) target = X[n, 64];

// Value in BTypeNext will be used to set PSTATE.BTYPE
if InGuardedPage then
    if n == 16 || n == 17 then
        BTypeNext = '01';
    else
        BTypeNext = '11';
else
    BTypeNext = '01';
BranchTo(target, BranchType_INDIR, FALSE);