fmov

Floating-point Move (Register)

FMOV <Dd>, <Dn>

Copies value between floating-point registers.

Details

Copies a 64-bit double-precision floating-point value from Dn to Dd without any conversion or modification. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.

Pseudocode Operation

Dd ← Dn

Example

FMOV d0, d1

Encoding

Binary Layout
0
0
0
11110
01
10000
00
10000
Rn
Rd
 
Format Float Data Proc
Opcode 0x1E604000
Extension F.P.

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dn
    First source 64-bit SIMD/FP register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F00FC00 FMOV <Vd>.<T>, #<imm> A64 0 | Q | 0 | 0111100000 | a | b | c | 1111 | 1 | 1 | d | e | f | g | h | Rd
0x0F00F400 FMOV <Vd>.<T>, #<imm> A64 0 | Q | 0 | 0111100000 | a | b | c | 1111 | 0 | 1 | d | e | f | g | h | Rd
0x6F00F400 FMOV <Vd>.2D, #<imm> A64 0 | 1 | 1 | 0111100000 | a | b | c | 1111 | 0 | 1 | d | e | f | g | h | Rd
0x05104000 FMOV <Zd>.<T>, <Pg>/M, #0.0 A64 00000101 | size | 01 | Pg | 0 | 1 | 0 | 00000000 | Zd
0x2538C000 FMOV <Zd>.<T>, #0.0 A64 00100101 | size | 111 | 0 | 0 | 011 | 0 | 00000000 | Zd
0x0510C000 FMOV <Zd>.<T>, <Pg>/M, #<const> A64 00000101 | size | 01 | Pg | 110 | imm8 | Zd
0x2539C000 FMOV <Zd>.<T>, #<const> A64 00100101 | size | 111 | 0 | 0 | 111 | 0 | imm8 | Zd
0x1EE04000 FMOV <Hd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 10000 | 00 | 10000 | Rn | Rd
0x1E204000 FMOV <Sd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 10000 | 00 | 10000 | Rn | Rd
0x1E604000 FMOV <Dd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 10000 | 00 | 10000 | Rn | Rd
0x1EE60000 FMOV <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 110 | 000000 | Rn | Rd
0x9EE60000 FMOV <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 00 | 110 | 000000 | Rn | Rd
0x1EE70000 FMOV <Hd>, <Wn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 111 | 000000 | Rn | Rd
0x1E270000 FMOV <Sd>, <Wn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 111 | 000000 | Rn | Rd

Description

Floating-point Move register without conversion. This instruction copies the floating-point value in the SIMD&FP source register to the SIMD&FP destination register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(128) result = 0<127:0>;

bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = operand;
V[d, 128] = result;