ldrexh

Load Register Exclusive Halfword (A32)

LDREXH<c> <Rt>, [<Rn>]

Loads a halfword and marks address as exclusive.

Details

Loads a 16-bit value from memory at the address in Rn and marks that address as exclusive for the current processor. The loaded halfword is zero-extended and placed in Rt. No condition flags are affected. This A32 instruction requires a matching STREXH to conditionally store; if the exclusive monitor is cleared, a subsequent STREXH will fail.

Pseudocode Operation

address ← Rn; Rt ← ZeroExtend(MemU[address, 2]); ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 2);

Example

LDREXH r3, [r1]

Encoding

Binary Layout
cond
00011
11
1
Rn
Rt
1
1
1
1
1001
1111
 
Format Load/Store Excl
Opcode 0x01F00F9F
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01F00F9F LDREXH{<c>}{<q>} <Rt>, [<Rn>] A32 cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111
0xE8D00F5F LDREXH{<c>}{<q>} <Rt>, [<Rn>] T32 11101000110 | 1 | Rn | Rt | 1111 | 01 | 01 | 1111

Description

Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address,2);
    R[t] = ZeroExtend(MemA[address,2], 32);