ldrexh

Load Register Exclusive Halfword (A32)

LDREXH<c> <Rt>, [<Rn>]

Loads a halfword and marks address as exclusive.

Pseudocode Operation

address ← Rn; Rt ← ZeroExtend(MemU[address, 2]); ExclusiveMonitorsMarkExclusive(address, ProcessorID(), 2);

Example

LDREXH r3, [r1]

Encoding

Binary Layout

cond

31:28

00011

27:23

11

22:21

1

20

Rn

19:16

Rt

15:12

1

11

1

10

1

9

1

8

1001

7:4

1111

3:0

 

Format Load/Store Excl

Opcode 0x01F00F9F

Extension A32 (Atomic)

Operands

• Rt
  Transfer general-purpose register (load/store)
• Rn
  First source / base general-purpose register

Related

Other forms of ldrexh

• ldrexh Load Register Exclusive Halfword (Thumb)

More in A32 (Atomic)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x01F00F9F	LDREXH{<c>}{<q>} <Rt>, [<Rn>]		A32		cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111
0xE8D00F5F	LDREXH{<c>}{<q>} <Rt>, [<Rn>]		T32		11101000110 | 1 | Rn | Rt | 1111 | 01 | 01 | 1111

Description

Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address,2);
    R[t] = ZeroExtend(MemA[address,2], 32);