stm.w

Store Multiple (Wide)

STM.W <Rn>{!}, <registers>

Thumb-2 32-bit Store Multiple.

Details

Store Multiple (32-bit Thumb-2 encoding) stores a list of general-purpose registers to consecutive memory locations starting at the address in Rn. If the writeback bit (!) is set, Rn is updated to point to the first address after the stored data. No flags are affected by this instruction. Execution is restricted to T32 (Thumb-2) state.

Pseudocode Operation

address ← Rn
for each register in registers (in increasing order):
  [address] ← register
  address ← address + 4
if writeback:
  Rn ← address

Example

STM.W r1!, registers

Encoding

Binary Layout
1110100
01
0
W
0
Rn
0
M
register_list
 
Format Thumb Store Multiple
Opcode 0xE8800000
Extension T32 (Thumb2)

Operands

  • Rn
    First source / base general-purpose register
  • registers
    List

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x08800000 STM{IA}{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 0 | 1 | 0 | W | 0 | Rn | register_list
0xC000 STM{IA}{<c>}{<q>} <Rn>!, <registers> T32 1100 | 0 | Rn | register_list
0xE8800000 STM{IA}{<c>}.W <Rn>{!}, <registers> T32 1110100 | 01 | 0 | W | 0 | Rn | 0 | M | register_list
0x08400000 STM{<amode>}{<c>}{<q>} <Rn>, <registers>^ A32 cond | 100 | P | U | 1 | 0 | 0 | Rn | register_list
0x08000000 STMDA{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 0 | 0 | 0 | W | 0 | Rn | register_list
0x09000000 STMDB{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 1 | 0 | 0 | W | 0 | Rn | register_list
0xE9000000 STMDB{<c>}{<q>} <Rn>{!}, <registers> T32 1110100 | 10 | 0 | W | 0 | Rn | 0 | M | register_list
0x09800000 STMIB{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 1 | 1 | 0 | W | 0 | Rn | register_list

Description

Store Multiple (Increment After, Empty Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the last of those locations can optionally be written back to the base register. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. Armv8.2 permits the deprecation of some Store Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC. For details of related system instructions see STM (User registers).

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    for i = 0 to 14
        if registers<i> == '1' then
            if i == n && wback && i != LowestSetBit(registers) then
                MemS[address,4] = bits(32) UNKNOWN;  // Only possible for encodings T1 and A1
            else
                MemS[address,4] = R[i];
            address = address + 4;
    if registers<15> == '1' then  // Only possible for encoding A1
        MemS[address,4] = PCStoreValue();
    if wback then R[n] = R[n] + 4*BitCount(registers);