decd

SVE Decrement Scalar by Doubleword Count

DECD <Xdn>, <pattern> {, MUL #<imm>}

Decrements a register by the number of active doublewords.

Pseudocode Operation

count ← CountActiveDoublewords(pattern)
multiplier ← imm4 if imm4 != 0 else 1
Xdn ← Xdn - (count * multiplier)

Example

DECD Xdn, pattern

Encoding

Binary Layout

00000100

31:24

1

23

1

22

11

21:20

imm4

19:16

11100

15:11

1

10

pattern

9:5

Rdn

4:0

 

Format SVE Inc/Dec

Opcode 0x04F0E400

Extension SVE

Operands

• Xdn
  Register
• pattern
  Predicate Pattern

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x04F0E400	DECD <Xdn>{, <pattern>{, MUL #<imm>}}		A64		00000100 | 1 | 1 | 11 | imm4 | 11100 | 1 | pattern | Rdn
0x04F0C400	DECD <Zdn>.D{, <pattern>{, MUL #<imm>}}		A64		00000100 | 1 | 1 | 11 | imm4 | 11000 | 1 | pattern | Zdn

Description

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

Operation

CheckSVEEnabled();
integer count = DecodePredCount(pat, esize);
constant integer VL = CurrentVL;
bits(64) operand1 = X[dn, 64];

X[dn, 64] = operand1 - (count * imm);