fcvtzs
Float to Signed Int (Round towards Zero)
Pseudocode Operation
No pseudocode available.
Encoding
Related
Other forms of fcvtzs
- fcvtzs SVE Floating-Point Convert to Signed Integer
- fcvtzs Floating-Point Convert to Signed Integer…
- fcvtzs Floating-point Convert to Signed Integer…
- fcvtzs Vector Floating-Point Convert to Signed…
Across architectures
Integer and Floating-Point Conversion : how x86, ARM, RISC-V, and PowerISA each do this.
More in SVE
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5F00FC00 | FCVTZS <V><d>, <V><n>, #<fbits> | A64 | 01 | 0 | 111110 | immh | immb | 11111 | 1 | Rn | Rd | ||
| 0x0F00FC00 | FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits> | A64 | 0 | Q | 0 | 011110 | immh | immb | 11111 | 1 | Rn | Rd | ||
| 0x5EF9B800 | FCVTZS <Hd>, <Hn> | A64 | 01 | 0 | 11110 | 1 | 1111001101 | 1 | 10 | Rn | Rd | ||
| 0x5EA1B800 | FCVTZS <V><d>, <V><n> | A64 | 01 | 0 | 11110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd | ||
| 0x0EF9B800 | FCVTZS <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | 1111001101 | 1 | 10 | Rn | Rd | ||
| 0x0EA1B800 | FCVTZS <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd | ||
| 0x1ED80000 | FCVTZS <Wd>, <Hn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x9ED80000 | FCVTZS <Xd>, <Hn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x1E180000 | FCVTZS <Wd>, <Sn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x9E180000 | FCVTZS <Xd>, <Sn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x1E580000 | FCVTZS <Wd>, <Dn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x9E580000 | FCVTZS <Xd>, <Dn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x1EF80000 | FCVTZS <Wd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd | ||
| 0x9EF80000 | FCVTZS <Xd>, <Hn> | A64 | 1 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd |
Description
Convert to the signed integer nearer to zero from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are sign-extended to fill each destination element.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
bits(esize) element = Elem[operand, e, esize];
bits(d_esize) res = FPToFixed(element<s_esize-1:0>, 0, unsigned, FPCR, rounding, d_esize);
Elem[result, e, esize] = Extend(res, esize, unsigned);
Z[d, VL] = result;