fmaxp
FMAXP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
Floating-point Maximum Pairwise.
Pseudocode Operation
No pseudocode available.
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5E30F800 | FMAXP H<d>, <Vn>.2H | A64 | 01 | 0 | 11110 | 0 | 0 | 11000 | 01111 | 10 | Rn | Rd | ||
| 0x7E30F800 | FMAXP <V><d>, <Vn>.<T> | A64 | 01 | 1 | 11110 | 0 | sz | 11000 | 01111 | 10 | Rn | Rd | ||
| 0x2E403400 | FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 110 | 1 | Rn | Rd | ||
| 0x2E20F400 | FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 1 | 01110 | 0 | sz | 1 | Rm | 11110 | 1 | Rn | Rd | ||
| 0x64168000 | FMAXP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01100100 | size | 010 | 11 | 0 | 100 | Pg | Zm | Zdn |
Description
Compute the maximum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. When FPCR.AH is 0, the behavior is as follows for each pairwise operation: When FPCR.AH is 1, the behavior is as follows for each pairwise operation:
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result = Z[dn, VL];
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
if IsEven(e) then
element1 = Elem[operand1, e + 0, esize];
element2 = Elem[operand1, e + 1, esize];
else
element1 = Elem[operand2, e - 1, esize];
element2 = Elem[operand2, e + 0, esize];
Elem[result, e, esize] = FPMax(element1, element2, FPCR);
Z[dn, VL] = result;