fmaxnmp
FMAXNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
Floating-point Max Num Pairwise.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
01100100
31:24
size
23:22
010
21:19
10
18:17
0
16
100
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
Related
More in SVE2
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5E30C800 | FMAXNMP H<d>, <Vn>.2H | A64 | 01 | 0 | 11110 | 0 | 0 | 11000 | 01100 | 10 | Rn | Rd | ||
| 0x7E30C800 | FMAXNMP <V><d>, <Vn>.<T> | A64 | 01 | 1 | 11110 | 0 | sz | 11000 | 01100 | 10 | Rn | Rd | ||
| 0x2E400400 | FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 000 | 1 | Rn | Rd | ||
| 0x2E20C400 | FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 1 | 01110 | 0 | sz | 1 | Rm | 11000 | 1 | Rn | Rd | ||
| 0x64148000 | FMAXNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01100100 | size | 010 | 10 | 0 | 100 | Pg | Zm | Zdn |
Description
Compute the maximum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector. Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation:
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result = Z[dn, VL];
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
if IsEven(e) then
element1 = Elem[operand1, e + 0, esize];
element2 = Elem[operand1, e + 1, esize];
else
element1 = Elem[operand2, e - 1, esize];
element2 = Elem[operand2, e + 0, esize];
Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
Z[dn, VL] = result;