fnmla

FNMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>

Floating-point Negated Multiply-Add.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout

01100101

31:24

size

23:22

20:16

12:10

9:5

Zda

4:0

Format SVE

Opcode 0x65204000

Extension SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x65204000	FNMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>		A64		01100101 \| size \| 1 \| Zm \| 0 \| 1 \| 0 \| Pg \| Zn \| Zda

Description

Multiply the corresponding active floating-point elements of the first and second source vectors and add to elements of the third source (addend) vector without intermediate rounding. Destructively place the negated results in the destination and third source (addend) vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) operand3 = Z[da, VL];
bits(VL) result;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element1 = Elem[operand1, e, esize];
        bits(esize) element2 = Elem[operand2, e, esize];
        bits(esize) element3 = Elem[operand3, e, esize];

        if op1_neg then element1 = FPNeg(element1, FPCR);
        if op3_neg then element3 = FPNeg(element3, FPCR);
        Elem[result, e, esize] = FPMulAdd(element3, element1, element2, FPCR);
    else
        Elem[result, e, esize] = Elem[operand3, e, esize];

Z[da, VL] = result;