ftsmul

FTSMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

FP Trig Starting Value Multiply.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01100101
31:24
size
23:22
0
21
Zm
20:16
000
15:13
01
12:11
1
10
Zn
9:5
Zd
4:0
 
Format SVE2
Opcode 0x65000C00
Extension SVE2

Related

More in SVE2

Reference

Instruction Forms

Encoding Instruction ISA Bit pattern
0x65000C00 FTSMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 01 | 1 | Zn | Zd

Description

The FTSMUL instruction calculates the initial value for the FTMAD instruction. The instruction squares each element in the first source vector and then sets the sign bit to a copy of bit 0 of the corresponding element in the second source register, and places the results in the destination vector. This instruction is unpredicated. To compute sin(x) or cos(x) the instruction is executed with elements of the first source vector set to x, adjusted to be in the range -π/4 < x ≤ π/4. The elements of the second source vector hold the corresponding value of the quadrant q number as an integer not a floating-point value. The value q satisfies the relationship (2q-1) × π/4 < x ≤ (2q+1) × π/4. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    bits(esize) element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPTrigSMul(element1, element2, FPCR);

Z[d, VL] = result;