incw

SVE Increment Scalar by Word Count

INCW <Xdn>, <pattern> {, MUL #<imm>}

Increments a register by the number of active words.

Details

Increments a 64-bit general-purpose register by the count of active words matching the specified pattern, optionally scaled by an immediate multiplier. The pattern defines which word positions are considered active. No condition flags are affected. This is an AArch64-only SVE instruction.

Pseudocode Operation

Xdn ← Xdn + (CountActiveWords(pattern) × (1 + imm4))

Example

INCW Xdn, pattern

Encoding

Binary Layout
00000100
1
0
11
imm4
11100
0
pattern
Rdn
 
Format SVE Inc/Dec
Opcode 0x04B0E000
Extension SVE

Operands

  • Xdn
    Register
  • pattern
    Predicate Pattern

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04B0E000 INCW <Xdn>{, <pattern>{, MUL #<imm>}} A64 00000100 | 1 | 0 | 11 | imm4 | 11100 | 0 | pattern | Rdn
0x04B0C000 INCW <Zdn>.S{, <pattern>{, MUL #<imm>}} A64 00000100 | 1 | 0 | 11 | imm4 | 11000 | 0 | pattern | Zdn

Description

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment the scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

Operation

CheckSVEEnabled();
integer count = DecodePredCount(pat, esize);
constant integer VL = CurrentVL;
bits(64) operand1 = X[dn, 64];

X[dn, 64] = operand1 + (count * imm);