ld1d

SVE Load Contiguous Doublewords

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>]

Loads doublewords from memory into a vector under predicate control.

Details

Loads contiguous doublewords from memory into a SVE vector register under predicate control. Each active predicate element loads one 64-bit value from the address sequence [Xn|SP + 8*i]. Inactive elements are zeroed (Z suffix semantics). No flags are affected.

Pseudocode Operation

for i = 0 to VL/64-1
  if Pg[i] == 1 then
    Zt.D[i] ← [Xn + 8*i]
  else
    Zt.D[i] ← 0

Example

LD1D p0/m/Z, [x1]

Encoding

Binary Layout
1100010
1
1
10
Zm
1
1
0
Pg
Rn
Zt
 
Format SVE Load
Opcode 0xC5C0C000
Extension SVE

Operands

  • Zt
    Dest Vector
  • Pg
    Predicate
  • Xn
    Base Addr

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA0406000 LD1D { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000100 | imm4 | 0 | 1 | 1 | PNg | Rn | Zt | 0
0xA040E000 LD1D { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000100 | imm4 | 1 | 1 | 1 | PNg | Rn | Zt | 0 | 0
0xA0006000 LD1D { <Zt1>.D-<Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] A64 10100000000 | Rm | 0 | 1 | 1 | PNg | Rn | Zt | 0
0xA000E000 LD1D { <Zt1>.D-<Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] A64 10100000000 | Rm | 1 | 1 | 1 | PNg | Rn | Zt | 0 | 0
0xA1406000 LD1D { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010100 | imm4 | 0 | 1 | 1 | PNg | Rn | T | 0 | Zt
0xA140E000 LD1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010100 | imm4 | 1 | 1 | 1 | PNg | Rn | T | 0 | 0 | Zt
0xA1006000 LD1D { <Zt1>.D, <Zt2>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] A64 10100001000 | Rm | 0 | 1 | 1 | PNg | Rn | T | 0 | Zt
0xA100E000 LD1D { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #3] A64 10100001000 | Rm | 1 | 1 | 1 | PNg | Rn | T | 0 | 0 | Zt
0xC5A0C000 LD1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] A64 1100010 | 1 | 1 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xA5E0A000 LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 111 | 1 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA5902000 LD1D { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 1 | 1 | 001 | imm4 | 001 | Pg | Rn | Zt
0xA5E04000 LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] A64 1010010 | 111 | 1 | Rm | 010 | Pg | Rn | Zt
0xA5808000 LD1D { <Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3] A64 1010010 | 1 | 1 | 00 | Rm | 100 | Pg | Rn | Zt
0xC5A04000 LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3] A64 1100010 | 1 | 1 | xs | 1 | Zm | 0 | 1 | 0 | Pg | Rn | Zt

Description

Gather load of doublewords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 8. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) offset;
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
boolean contiguous = FALSE;
boolean nontemporal = FALSE;
boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    offset = Z[m, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned);
        bits(64) addr = GenerateAddress(base, off << scale, accdesc);
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);

Z[t, VL] = result;