bics

Bitwise Bit Clear and Set Flags (64-bit)

BICS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

Performs BIC and updates flags (64-bit).

Details

64-bit bitwise AND NOT with flag update: Xd ← Xn AND NOT (Xm, optionally shifted), then updates NZCV condition flags based on the result. The C and V flags are cleared. This is an AArch64-only instruction.

Pseudocode Operation

operand2 ← DecodeShift(Xm, shift, amount)
Xd ← Xn AND NOT operand2
N ← Xd[63]
Z ← (Xd == 0)
C ← 0
V ← 0

Example

BICS x0, x1, x2

Encoding

Binary Layout
1
11
01010
shift
1
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0xEA200000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • Xm
    Second source / offset 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x6A200000 BICS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 11 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0xEA200000 BICS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 11 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x25404010 BICS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 1 | 00 | Pm | 01 | Pg | 0 | Pn | 1 | Pd

Description

Bitwise Bit Clear (shifted register), setting flags, performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 AND operand2;
PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00';

X[d, datasize] = result;