addg
Add with Tag
ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4>
Adds an immediate to an address, modifying the Allocation Tag (MTE).
Details
Adds a scaled immediate offset (uimm6 × 16) to an address in the source register and simultaneously updates the Memory Tagging Extension (MTE) Allocation Tag in bits [59:56] by adding uimm4. The result is stored in the destination register. This is an AArch64-only instruction that modifies both address and tag atomically. No condition flags are affected.
Pseudocode Operation
Example
ADDG x0, x1, #8, #3
Encoding
Binary Layout
1
0
0
1000110
uimm6
00
uimm4
Xn
Xd
Operands
-
Xd
Destination 64-bit integer register -
Xn
First source / base 64-bit integer register -
uimm6
Address Offset -
uimm4
Tag Offset
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x91800000 | ADDG <Xd|SP>, <Xn|SP>, #<uimm6>, #<uimm4> | A64 | 1 | 0 | 0 | 1000110 | uimm6 | 00 | uimm4 | Xn | Xd |
Description
Add with Tag adds an immediate value scaled by the Tag granule to the address in the source register, modifies the Logical Address Tag of the address using an immediate value, and writes the result to the destination register. Tags specified in GCR_EL1.Exclude are excluded from the possible outputs when modifying the Logical Address Tag.
Operation
bits(64) operand1 = if n == 31 then SP[] else X[n, 64];
bits(4) start_tag = AArch64.AllocationTagFromAddress(operand1);
bits(16) exclude = GCR_EL1.Exclude;
bits(64) result;
bits(4) rtag;
if AArch64.AllocationTagAccessIsEnabled(PSTATE.EL) then
rtag = AArch64.ChooseNonExcludedTag(start_tag, uimm4, exclude);
else
rtag = '0000';
(result, -) = AddWithCarry(operand1, offset, '0');
result = AArch64.AddressWithAllocationTag(result, rtag);
if d == 31 then
SP[] = result;
else
X[d, 64] = result;