csinv

Conditional Select Invert

CSINV <Wd>, <Wn>, <Wm>, <cond>

Selects Wn if cond true, else NOT Wm.

Pseudocode Operation

if ConditionHolds(cond) then
  Wd ← Wn
else
  Wd ← ~Wm

Example

CSINV w0, w1, w2, cond

Encoding

Binary Layout

0

31

1

30

0

29

11010100

28:21

Rm

20:16

cond

15:12

0

11

0

10

Rn

9:5

Rd

4:0

 

Format Cond Select

Opcode 0x5A800000

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  True Src
• Wm
  False Src
• cond
  Cond

Related

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x5A800000	CSINV <Wd>, <Wn>, <Wm>, <cond>		A64		0 | 1 | 0 | 11010100 | Rm | cond | 0 | 0 | Rn | Rd
0xDA800000	CSINV <Xd>, <Xn>, <Xm>, <cond>		A64		1 | 1 | 0 | 11010100 | Rm | cond | 0 | 0 | Rn | Rd

Description

Conditional Select Invert returns, in the destination register, the value of the first source register if the condition is TRUE, and otherwise returns the bitwise inversion value of the second source register.

Operation

bits(datasize) result;
if ConditionHolds(cond) then
    result = X[n, datasize];
else
    result = X[m, datasize];
    result = NOT(result);

X[d, datasize] = result;