eon

Bitwise Exclusive OR NOT (64-bit)

EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>}

XORs 64-bit register with NOT of shifted register.

Details

64-bit exclusive OR NOT: Xd ← Xn XOR NOT (Xm, optionally shifted). The second operand is shifted before the NOT operation is applied. NZCV flags are not affected. This is an AArch64-only instruction.

Pseudocode Operation

operand2 ← DecodeShift(Xm, shift, amount)
Xd ← Xn XOR NOT operand2

Example

EON x0, x1, x2

Encoding

Binary Layout
1
10
01010
shift
1
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0xCA200000
Extension Base

Operands

  • Xd
    Destination 64-bit integer register
  • Xn
    First source / base 64-bit integer register
  • Xm
    Second source / offset 64-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x4A200000 EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 10 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0xCA200000 EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 10 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x05400000 EON <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 0 | 1 | 0000 | imm13 | Zdn

Description

Bitwise Exclusive-OR NOT (shifted register) performs a bitwise exclusive-OR NOT of a register value and an optionally-shifted register value, and writes the result to the destination register.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 EOR operand2;

X[d, datasize] = result;