umulh
Unsigned Multiply High
UMULH <Xd>, <Xn>, <Xm>
Multiplies two 64-bit registers, keeps high 64 bits (Unsigned).
Details
Multiplies the unsigned 64-bit values in Xn and Xm, treating both as unsigned integers, and stores the high 64 bits of the 128-bit product in Xd. This is AArch64-only. No arithmetic flags are affected.
Pseudocode Operation
temp ← Xn × Xm; Xd ← temp[127:64]
Example
UMULH x0, x1, x2
Encoding
Binary Layout
1
00
11011
1
10
Rm
0
11111
Rn
Rd
Operands
-
Xd
Destination 64-bit integer register -
Xn
First source / base 64-bit integer register -
Xm
Second source / offset 64-bit integer register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x9BC07C00 | UMULH <Xd>, <Xn>, <Xm> | A64 | 1 | 00 | 11011 | 1 | 10 | Rm | 0 | 11111 | Rn | Rd | ||
| 0x04130000 | UMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 0100 | 1 | 1 | 000 | Pg | Zm | Zdn | ||
| 0x04206C00 | UMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 1 | Zm | 0110 | 1 | 1 | Zn | Zd |
Description
Unsigned Multiply High multiplies two 64-bit register values, and writes bits[127:64] of the 128-bit result to the 64-bit destination register.
Operation
bits(64) operand1 = X[n, 64]; bits(64) operand2 = X[m, 64]; integer result; result = Int(operand1, TRUE) * Int(operand2, TRUE); X[d, 64] = result<127:64>;