uxtab16

Unsigned Extend and Add Byte 16

UXTAB16<c> <Rd>, <Rn>, <Rm> {, <rotation>}

Zero-extends two bytes and adds to two halfwords.

Pseudocode Operation

rotated ← ROR(Rm, rotation)
byte0 ← rotated[7:0]
byte1 ← rotated[15:8]
zero_ext0 ← ZeroExtend(byte0, 16)
zero_ext1 ← ZeroExtend(byte1, 16)
Rd[15:0] ← Rn[15:0] + zero_ext0
Rd[31:16] ← Rn[31:16] + zero_ext1

Example

UXTAB16 r0, r1, r2

Encoding

Binary Layout

cond

31:28

01101

27:23

1

22

00

21:20

Rn

19:16

Rd

15:12

rotate

11:10

0

9

0

8

0111

7:4

Rm

3:0

 

Format Data Proc

Opcode 0x06C00070

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  Accumulator
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x06C00070	UXTAB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}		A32		cond | 01101 | 1 | 00 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm
0xFA30F080	UXTAB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}		T32		111110100 | 01 | 1 | Rn | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d]<15:0>  = R[n]<15:0> + ZeroExtend(rotated<7:0>, 16);
    R[d]<31:16> = R[n]<31:16> + ZeroExtend(rotated<23:16>, 16);