umlal

Unsigned Multiply Accumulate Long (A32)

UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>

Unsigned (Rn * Rm) + 64-bit Accumulator.

Details

Unsigned multiply of Rn and Rm, then add the 64-bit result to the 64-bit accumulator formed by RdHi:RdLo, storing the result back in RdHi:RdLo. If the S bit is set, the N and Z flags are updated based on the result; C and V are unaffected. This is an A32 instruction and does not execute in AArch64 or T32 states.

Pseudocode Operation

accumulator ← (RdHi << 32) | RdLo
product ← (Rn × Rm)
result ← accumulator + product
RdHi ← result[63:32]
RdLo ← result[31:0]
if S == 1 then
  N ← result[63]
  Z ← (result == 0)
endif

Example

UMLAL r1, r0, r1, r2

Encoding

Binary Layout
cond
0000
101
0
RdHi
RdLo
Rm
1001
Rn
 
Format Multiply
Opcode 0x00A00090
Extension A32 (Base)

Operands

  • RdLo
    Low
  • RdHi
    High
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x00A00090 UMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> A32 cond | 0000 | 101 | 0 | RdHi | RdLo | Rm | 1001 | Rn
0xFBE00000 UMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> T32 111110111 | 110 | Rn | RdLo | RdHi | 0000 | Rm

Description

Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = UInt(R[n]) * UInt(R[m]) + UInt(R[dHi]:R[dLo]);
    R[dHi] = result<63:32>;
    R[dLo] = result<31:0>;
    if setflags then
        PSTATE.N = result<63>;
        PSTATE.Z = IsZeroBit(result<63:0>);
        // PSTATE.C, PSTATE.V unchanged