frsqrte

Vector Floating-Point Reciprocal Sqrt Estimate

FRSQRTE <Vd>.<T>, <Vn>.<T>

Estimates reciprocal square root (1/sqrt(x)).

Pseudocode Operation

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ReciprocalSquareRootEstimate(Vn[i])  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← ReciprocalSquareRootEstimate(Vn[i])  // 64-bit float

Example

FRSQRTE v0.4s.T, v1.4s.T

Encoding

Binary Layout

0

31

Q

30

1

29

01110

28:24

1

23

111100

22:17

11101

16:12

10

11:10

Rn

9:5

Rd

4:0

 

Format SIMD Two Register

Opcode 0x2EF9D800

Extension NEON (SIMD)

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x7EF9D800	FRSQRTE <Hd>, <Hn>		A64		01 | 1 | 11110 | 1 | 111100 | 11101 | 10 | Rn | Rd
0x7EA1D800	FRSQRTE <V><d>, <V><n>		A64		01 | 1 | 111101 | sz | 10000 | 11101 | 10 | Rn | Rd
0x2EF9D800	FRSQRTE <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 01110 | 1 | 111100 | 11101 | 10 | Rn | Rd
0x2EA1D800	FRSQRTE <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 011101 | sz | 10000 | 11101 | 10 | Rn | Rd
0x650F3000	FRSQRTE <Zd>.<T>, <Zn>.<T>		A64		01100101 | size | 00111 | 1 | 001100 | Zn | Zd

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

if elements == 1 then
    CheckFPEnabled64();
else
    CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];

bits(esize) element;
boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);

V[d, 128] = result;