bxj

Branch and Exchange Jazelle (A32)

BXJ<c> <Rm>

Legacy instruction to enter Jazelle state (Now behaves like BX).

Pseudocode Operation

next_address ← Rm
if next_address[0] == 1 then
  CPSR.T ← 1
else
  CPSR.T ← 0
PC ← next_address AND NOT(0x1)

Example

BXJ r2

Encoding

Binary Layout

cond

31:28

00010010

27:20

1

19

1

18

1

17

1

16

1

15

1

14

1

13

1

12

1

11

1

10

1

9

1

8

0010

7:4

Rm

3:0

 

Format Branch

Opcode 0x012FFF20

Extension A32 (Legacy)

Operands

• Rm
  Second source / offset general-purpose register

Related

More in A32 (Legacy)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x012FFF20	BXJ{<c>}{<q>} <Rm>		A32		cond | 00010010 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0010 | Rm
0xF3C08F00	BXJ{<c>}{<q>} <Rm>		T32		111100111100 | Rm | 10 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0

Description

Branch and Exchange, previously Branch and Exchange Jazelle. BXJ behaves as a BX instruction, see BX. This means it causes a branch to an address and instruction set specified by a register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    BXWritePC(R[m], BranchType_INDIR);