bxj

Branch and Exchange Jazelle (A32)

BXJ<c> <Rm>

Legacy instruction to enter Jazelle state (Now behaves like BX).

Details

Legacy instruction that branches to the address in Rm with exchange (Thumb/ARM mode switching based on bit [0] of Rm). In current ARMv8 architecture, BXJ behaves identically to BX due to Jazelle being obsolete. Bit [0] of Rm determines the target state (0=ARM, 1=Thumb). No condition flags are affected. Execution state: A32 only.

Pseudocode Operation

next_address ← Rm
if next_address[0] == 1 then
  CPSR.T ← 1
else
  CPSR.T ← 0
PC ← next_address AND NOT(0x1)

Example

BXJ r2

Encoding

Binary Layout
cond
00010010
1
1
1
1
1
1
1
1
1
1
1
1
0010
Rm
 
Format Branch
Opcode 0x012FFF20
Extension A32 (Legacy)

Operands

  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x012FFF20 BXJ{<c>}{<q>} <Rm> A32 cond | 00010010 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0010 | Rm
0xF3C08F00 BXJ{<c>}{<q>} <Rm> T32 111100111100 | Rm | 10 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0

Description

Branch and Exchange, previously Branch and Exchange Jazelle. BXJ behaves as a BX instruction, see BX. This means it causes a branch to an address and instruction set specified by a register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    BXWritePC(R[m], BranchType_INDIR);