vfnms

Vector Fused Negated Multiply Subtract

VFNMS<c>.F32 <Sd>, <Sn>, <Sm>

Computes Vd = -Vd + (Vn * Vm).

Details

The Vector Fused Negated Multiply Subtract instruction computes Vd = -Vd + (Vn * Vm).

Pseudocode Operation

Sd ← Sn - Sm
// Flags affected: N, Z, C, V

Example

VFNMS.F32 s0, s1, s2

Encoding

Binary Layout
11101110
1
D
0
Vn
Vd
1010
N
1
M
Vm
 
Format VFP Arith
Opcode 0xEE900A40
Extension VFPv4 (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    First source 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register