vfnms

Vector Fused Negated Multiply Subtract

VFNMS<c>.F32 <Sd>, <Sn>, <Sm>

Computes Vd = -Vd + (Vn * Vm).

Details

Vector Fused Negated Multiply Subtract computes the negation of the destination plus the product of two operands: Sd = -Sd + (Sn * Sm). This is a single fused operation that performs multiplication and subtraction with only one rounding step, improving precision over separate operations. The instruction is available in VFPv4 and operates on 32-bit single-precision floating-point values. Condition flags (N, Z, C, V) are not affected; floating-point exception flags may be set based on the result.

Pseudocode Operation

Sd ← -Sd + (Sn * Sm)

Example

VFNMS.F32 s0, s1, s2

Encoding

Binary Layout
cond
1110
1
D
01
Vn
Vd
10
10
N
0
M
0
Vm
 
Format VFP Arith
Opcode 0x0E900A00
Extension VFPv4 (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    First source 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E900900 VFNMS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0E900A00 VFNMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> A32 cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0E900B00 VFNMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> A32 cond | 1110 | 1 | D | 01 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xEE900900 VFNMS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm> T32 11101110 | 1 | D | 01 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEE900A00 VFNMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm> T32 11101110 | 1 | D | 01 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEE900B00 VFNMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm> T32 11101110 | 1 | D | 01 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm

Description

Vector Fused Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register. The instruction does not round the result of the multiply before the addition. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
    case esize of
        when 16
            op16 = if op1_neg then FPNeg(S[n]<15:0>) else S[n]<15:0>;
            S[d] = Zeros(16) : FPMulAdd(FPNeg(S[d]<15:0>), op16, S[m]<15:0>, FPSCR[]);
        when 32
            op32 = if op1_neg then FPNeg(S[n]) else S[n];
            S[d] = FPMulAdd(FPNeg(S[d]), op32, S[m], FPSCR[]);
        when 64
            op64 = if op1_neg then FPNeg(D[n]) else D[n];
            D[d] = FPMulAdd(FPNeg(D[d]), op64, D[m], FPSCR[]);