vstr

Vector Store Register (VFP)

VSTR<c> <Sd>, [<Rn>, #+/-<imm>]

Stores a floating-point register to memory.

Pseudocode Operation

offset ← ZeroExtend(imm8) << 2
if U == 1 then
  address ← Rn + offset
else
  address ← Rn - offset
[address] ← Sd

Example

VSTR s0, [r1, #+/-#16]

Encoding

Binary Layout

cond

31:28

110

27:25

1

24

U

23

D

22

0

21

0

20

Rn

19:16

Vd

15:12

10

11:10

10

9:8

imm8

7:0

 

Format VFP Store

Opcode 0x0D000A00

Extension VFP (Float)

Operands

• Sd
  Destination 32-bit floating-point register
• Rn
  First source / base general-purpose register
• imm
  Signed immediate value

Related

More in VFP (Float)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0D000900	VSTR{<c>}{<q>}.16 <Sd>, [<Rn>{, #{+/-}<imm>}]		A32		cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 01 | imm8
0x0D000A00	VSTR{<c>}{<q>}{.32} <Sd>, [<Rn>{, #{+/-}<imm>}]		A32		cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 10 | imm8
0x0D000B00	VSTR{<c>}{<q>}{.64} <Dd>, [<Rn>{, #{+/-}<imm>}]		A32		cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 11 | imm8
0xED000900	VSTR{<c>}{<q>}.16 <Sd>, [<Rn>{, #{+/-}<imm>}]		T32		1110110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 01 | imm8
0xED000A00	VSTR{<c>}{<q>}{.32} <Sd>, [<Rn>{, #{+/-}<imm>}]		T32		1110110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 10 | imm8
0xED000B00	VSTR{<c>}{<q>}{.64} <Dd>, [<Rn>{, #{+/-}<imm>}]		T32		1110110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 11 | imm8

Description

Store SIMD&FP register stores a single register from the Advanced SIMD and floating-point register file to memory, using an address from a general-purpose register, with an optional offset. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    address = if add then (R[n] + imm32) else (R[n] - imm32);
    case esize of
        when 16
            MemA[address,2] = S[d]<15:0>;
        when 32
            MemA[address,4] = S[d];
        when 64
            // Store as two word-aligned words in the correct order for current endianness.
            if BigEndian(AccessType_ASIMD) then
                MemA[address,4]   = D[d]<63:32>;
                MemA[address+4,4] = D[d]<31:0>;
            else
                MemA[address,4]   = D[d]<31:0>;
                MemA[address+4,4] = D[d]<63:32>;