vstr

Vector Store Register (VFP)

VSTR<c> <Sd>, [<Rn>, #+/-<imm>]

Stores a floating-point register to memory.

Details

Stores a single-precision floating-point value from a VFP register to memory using a register-relative address with an optional offset. The memory access uses the address [Rn ± (imm8 << 2)]. Executed in A32/T32 with VFP extension; no condition flags are affected.

Pseudocode Operation

offset ← ZeroExtend(imm8) << 2
if U == 1 then
  address ← Rn + offset
else
  address ← Rn - offset
[address] ← Sd

Example

VSTR s0, [r1, #+/-#16]

Encoding

Binary Layout
cond
110
1
U
D
0
0
Rn
Vd
10
10
imm8
 
Format VFP Store
Opcode 0x0D000A00
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0D000900 VSTR{<c>}{<q>}.16 <Sd>, [<Rn>{, #{+/-}<imm>}] A32 cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 01 | imm8
0x0D000A00 VSTR{<c>}{<q>}{.32} <Sd>, [<Rn>{, #{+/-}<imm>}] A32 cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 10 | imm8
0x0D000B00 VSTR{<c>}{<q>}{.64} <Dd>, [<Rn>{, #{+/-}<imm>}] A32 cond | 110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 11 | imm8
0xED000900 VSTR{<c>}{<q>}.16 <Sd>, [<Rn>{, #{+/-}<imm>}] T32 1110110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 01 | imm8
0xED000A00 VSTR{<c>}{<q>}{.32} <Sd>, [<Rn>{, #{+/-}<imm>}] T32 1110110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 10 | imm8
0xED000B00 VSTR{<c>}{<q>}{.64} <Dd>, [<Rn>{, #{+/-}<imm>}] T32 1110110 | 1 | U | D | 0 | 0 | Rn | Vd | 10 | 11 | imm8

Description

Store SIMD&FP register stores a single register from the Advanced SIMD and floating-point register file to memory, using an address from a general-purpose register, with an optional offset. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    address = if add then (R[n] + imm32) else (R[n] - imm32);
    case esize of
        when 16
            MemA[address,2] = S[d]<15:0>;
        when 32
            MemA[address,4] = S[d];
        when 64
            // Store as two word-aligned words in the correct order for current endianness.
            if BigEndian(AccessType_ASIMD) then
                MemA[address,4]   = D[d]<63:32>;
                MemA[address+4,4] = D[d]<31:0>;
            else
                MemA[address,4]   = D[d]<31:0>;
                MemA[address+4,4] = D[d]<63:32>;