and.w

Bitwise AND (Wide)

AND.W <Rd>, <Rn>, <Operand2>

Thumb-2 32-bit AND.

Details

Performs a bitwise AND of Rn and the shifted Operand2, storing the result in Rd. In Thumb-2, this is a 32-bit instruction that can update the condition flags (N, Z, C) when the S bit is set; V is unaffected. The operand2 can be a register with optional shift or an immediate value.

Pseudocode Operation

result ← Rn AND Operand2
Rd ← result
if S == 1 then
  CPSR.N ← result[31]
  CPSR.Z ← (result == 0)
  CPSR.C ← CarryOut(Operand2)
else
  CPSR.C ← CPSR.C

Example

AND.W r0, r1, r2

Encoding

Binary Layout
1110101
0000
0
Rn
0
imm3
Rd
imm2
stype
Rm
 
Format Thumb2 Data Proc
Opcode 0xEA000000
Extension T32 (Thumb2)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Operand2
    Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x02000000 AND{<c>}{<q>} {<Rd>,} <Rn>, #<const> A32 cond | 0010 | 000 | 0 | Rn | Rd | imm12
0xF0000000 AND{<c>}{<q>} {<Rd>,} <Rn>, #<const> T32 11110 | i | 0 | 0000 | 0 | Rn | 0 | imm3 | Rd | imm8
0x00000060 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX A32 cond | 0000 | 000 | 0 | Rn | Rd | 00000 | 11 | 0 | Rm
0x00000000 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>} A32 cond | 0000 | 000 | 0 | Rn | Rd | imm5 | stype | 0 | Rm
0x4000 AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> T32 010000 | 0000 | Rm | Rdn
0xEA000030 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX T32 1110101 | 0000 | 0 | Rn | 0 | 000 | Rd | 00 | 11 | Rm
0xEA000000 AND<c>.W {<Rd>,} <Rn>, <Rm> T32 1110101 | 0000 | 0 | Rn | 0 | imm3 | Rd | imm2 | stype | Rm
0x00000010 AND{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> A32 cond | 0000 | 000 | 0 | Rn | Rd | Rs | 0 | stype | 1 | Rm

Description

Bitwise AND (register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the ANDS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. Arm deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = R[n] AND shifted;
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged