saddl

Signed Add Long

SADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts>

Adds lower/upper halves of signed vectors, producing wider result (Widening).

Details

The Signed Add Long instruction adds lower/upper halves of signed vectors, producing wider result (Widening).

Pseudocode Operation

Vd ← Vn + Vm
// Flags affected: N, Z, C, V

Example

SADDL v0.4s.Td, v1.4s.Ts, v2.4s.Ts

Encoding

Binary Layout
0
Q
001110
size
1
0000
Rm
0000
Rn
Rd
 
Format SIMD Three Register Diff
Opcode 0x0E200000
Extension NEON (SIMD)

Operands

  • Vd
    Dest (Wide)
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register