saddl

Signed Add Long

SADDL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts>

Adds lower/upper halves of signed vectors, producing wider result (Widening).

Details

Adds corresponding signed integer elements from the lower (or upper, depending on Q) halves of two narrow NEON vectors, producing a vector of wider elements. Q=0 operates on lower halves; Q=1 operates on upper halves. The result is placed in the wider destination vector. No condition flags are affected; the instruction is AArch64 NEON-only with signed saturation not applied (wrapping on overflow).

Pseudocode Operation

if Q == 0 then
  half ← "lower"
else
  half ← "upper"
for i = 0 to (length(Vd) / element_width(Td)) - 1 do
  Vn_element ← extract_half(Vn[i], half)
  Vm_element ← extract_half(Vm[i], half)
  Vd[i] ← signed_add(Vn_element, Vm_element)
N ← unaffected; Z ← unaffected; C ← unaffected; V ← unaffected

Example

SADDL v0.4s.Td, v1.4s.Ts, v2.4s.Ts

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
00
0
000
Rn
Rd
 
Format SIMD Three Register Diff
Opcode 0x0E200000
Extension NEON (SIMD)

Operands

  • Vd
    Dest (Wide)
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E200000 SADDL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 00 | 0 | 000 | Rn | Rd

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values. The SADDL instruction extracts each source vector from the lower half of each source register. The SADDL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part, datasize];
bits(datasize) operand2 = Vpart[m, part, datasize];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d, 2*datasize] = result;